SPRSP96A March 2024 – September 2024 TDA4AEN-Q1 , TDA4VEN-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
SIGNAL NAME [1] | PIN TYPE [2] | DESCRIPTION [3] | AMW PIN [4] |
---|---|---|---|
AUDIO_EXT_REFCLK0 | IO | External clock input to McASP or output from McASP | E22, F23, W23 |
AUDIO_EXT_REFCLK1 | IO | External clock input to McASP or output from McASP | B21, C26, N24 |
AUDIO_EXT_REFCLK2 | IO | External clock input to McASP or output from McASP | W26 |
CLKOUT0 | O | RMII Clock Output (50 MHz). This pin is used for clock source to the external RMII PHY and must also be routed back to the respective RMII[x]_REF_CLK pin for proper device operation. | A23, AA22, AF24 |
EXTINTn | I | External Interrupt | B23 |
EXT_REFCLK1 | I | External clock input to Main Domain | A23 |
MAIN_ERRORn | IO | Error signal output from MAIN Domain ESM | B25, C20, N25 |
OBSCLK0 | O | Main Domain Observation clock output for test and debug purposes only | V27 |
OBSCLK1 | O | Main Domain Observation clock output for test and debug purposes only | D23 |
PORz_OUT | O | Main Domain POR status output | D27 |
RESETSTATz | O | Main Domain warm reset status output | E27 |
RESET_REQz | I | Main Domain external warm reset request input | E26 |
SYNC0_OUT | O | CPTS Time Stamp Generator Bit 0 Output from Time Sync Router | D23 |
SYNC1_OUT | O | CPTS Time Stamp Generator Bit 1 Output from Time Sync Router | A23 |
SYNC2_OUT | O | CPTS Time Stamp Generator Bit 2 Output from Time Sync Router | D22 |
SYNC3_OUT | O | CPTS Time Stamp Generator Bit 3 Output from Time Sync Router | C22 |
SYSCLKOUT0 | O | Main Domain system clock output (divided by 4) for test and debug purposes only | A23 |