SPRSP96A March 2024 – September 2024 TDA4AEN-Q1 , TDA4VEN-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Table 6-1 defines the maximum operating frequency of the clocks for each device speed grade and Table 6-2 defines the only valid Operating Performance Points (OPPs) for the device subsystem and core clocks..
Speed Grade |
VDD_CORE (V)(1) |
MAXIMUM OPERATING FREQUNCY (MHz) | MAXIMUM DATA RATE (MT/s)(2) | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
A53SS (Cortex-A53x) |
C7/MMA | R5FSS0 | MAIN DOMAIN SYSCLK | MCU R5F | MCU DOMAIN SYSCLK | DEVICE MGR R5F | DEVICE MGR DOMAIN CLK | HSM | GPU | VPAC | DMPAC | VPU | LPDDR4 | ||
J | 0.75 | 1250 | 912.5 | 800 | 500 | 800 | 400 | 800 | 400 | 400 | 720 | 600 | 428.5 | 500 | 3200 to 3733 |
K | 0.85 | 1400 | 1000 | 800 | 3466 to 4000 |
OPP | A53SS(1) | C7/MMA | FIXED OPERATING FREQUENCY OPTIONS (MHz)(2) | MT/s(3) | ||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
R5FSS0 | MAIN DOMAIN SYSCLK | MCU R5F | MCU DOMAIN SYSCLK | DEVICE MGR R5F | DEVICE MGR DOMAIN CLK | HSM | GPU | VPAC | DMPAC | VPU | LPDDR4 | |||
High |
From PLL BP to Speed Grade Max | From PLL BP to Speed Grade Max | 800 | 500 | 800 | 400 | 800 | 400 | 400 | Speed Grade Max | 600 | 428.5 | 500, 400, 200, or 100 |
From PLL BP to Speed Grade Max |
Low |
400 | 250 | 400 | 200 | 400 | 133 | 133 |