SPRSP96A March 2024 – September 2024 TDA4AEN-Q1 , TDA4VEN-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Read and write data valid windows will shift due to variation in process, voltage, temperature, and operating frequency. A data training method may be implemented to dynamically configure optimal read and write timing. Implementing data training enables proper operation across temperature with a specific process, voltage, and frequency operating condition, while achieving a higher operating frequency.
Data transmit and receive timing parameters are not defined for the data training use case since they are dynamically adjusted based on the operating condition.
Table 6-113 defines DLL delays required for OSPI0 with Data Training. Table 6-114, Figure 6-95, Figure 6-96, Table 6-115, Figure 6-97, and Figure 6-98 present timing requirements and switching characteristics for OSPI0 with Data Training.
MODE | OSPI_PHY_CONFIGURATION_REG BIT FIELD | DELAY VALUE |
---|---|---|
Transmit | ||
All modes | PHY_CONFIG_TX_DLL_DELAY_FLD | (1) |
Receive | ||
All modes | PHY_CONFIG_RX_DLL_DELAY_FLD | (2) |
NO. | MODE | MIN | MAX | UNIT | ||
---|---|---|---|---|---|---|
O15 | tsu(D-LBCLK) | Setup time, OSPI0_D[7:0] valid before active OSPI0_DQS edge | DDR with DQS | (1) | ns | |
O16 | th(LBCLK-D) | Hold time, OSPI0_D[7:0] valid after active OSPI0_DQS edge | DDR with DQS | (1) | ns | |
O21 | tsu(D-LBCLK) | Setup time, OSPI0_D[7:0] valid before active OSPI0_DQS edge | SDR with External Board Loopback | (1) | ns | |
O22 | th(LBCLK-D) | Hold time, OSPI0_D[7:0] valid after active OSPI0_DQS edge | SDR with External Board Loopback | (1) | ns | |
tDVW | Data valid window (O15 + O16) | 1.8V, DDR with DQS | 1.6 | ns | ||
3.3V, DDR with DQS | 2.2 | ns | ||||
Data valid window (O21 + O22) | 1.8V, SDR with External Board Loopback | 2.3 | ns | |||
3.3V, SDR with External Board Loopback | 2.9 | ns |
NO. | PARAMETER | MODE | MIN | MAX | UNIT | |
---|---|---|---|---|---|---|
O1 | tc(CLK) | Cycle time, OSPI0_CLK | 1.8V, DDR | 6.0 | 10 | ns |
3.3V, DDR | 7.5 | 10 | ns | |||
O7 | 1.8V, SDR | 6.0 | 10 | ns | ||
3.3V, SDR | 7.5 | 10 | ns | |||
O2 | tw(CLKL) | Pulse duration, OSPI0_CLK low | DDR | ((0.475P(1)) - 0.3) | ns | |
O8 | SDR | |||||
O3 | tw(CLKH) | Pulse duration, OSPI0_CLK high | DDR | ((0.475P(1)) - 0.3) | ns | |
O9 | SDR | |||||
O4 | td(CSn-CLK) | Delay time, OSPI0_CSn[3:0] active edge to OSPI0_CLK rising edge | DDR | ((0.475P(1)) + (0.975M(2)R(4)) + (0.04TD(5)) - 1) | ((0.525P(1)) + (1.025M(2)R(4)) + (0.11TD(5)) + 1) | ns |
O10 | SDR | |||||
O5 | td(CLK-CSn) | Delay time, OSPI0_CLK rising edge to OSPI0_CSn[3:0] inactive edge | DDR | ((0.475P(1)) + (0.975N(3)R(4)) - (0.04TD(5)) - 1) | ((0.525P(1)) + (1.025N(3)R(4)) - (0.11TD(5)) + 1) | ns |
O11 | SDR | |||||
O6 | td(CLK-D) | Delay time, OSPI0_CLK active edge to OSPI0_D[7:0] transition | DDR | (6) | (6) | ns |
O12 | SDR | |||||
tDIVW | Data invalid window (O6 Max - Min) | DDR | 1.6 | ns | ||
Data invalid window (O12 Max - Min) | SDR |