SPRSP96A March 2024 – September 2024 TDA4AEN-Q1 , TDA4VEN-Q1
PRODUCTION DATA
Refer to the PDF data sheet for device specific package drawings
Table 6-31, Table 6-32, Figure 6-28, Table 6-33, Figure 6-29, Table 6-34, and Figure 6-30 present timing conditions, timing requirements, and switching characteristics for CPSW3G RMII.
PARAMETER | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
INPUT CONDITIONS | |||||
SRI | Input slew rate | VDD(1) = 1.8V | 0.18 | 0.54 | V/ns |
VDD(1) = 3.3V | 0.4 | 1.2 | V/ns | ||
OUTPUT CONDITIONS | |||||
CL | Output load capacitance | 3 | 25 | pF |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
RMII1 | tc(REF_CLK) | Cycle time, RMII[x]_REF_CLK | 19.999 | 20.001 | ns |
RMII2 | tw(REF_CLKH) | Pulse Duration, RMII[x]_REF_CLK High | 7 | 13 | ns |
RMII3 | tw(REF_CLKL) | Pulse Duration, RMII[x]_REF_CLK Low | 7 | 13 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
RMII4 | tsu(RXD-REF_CLK) | Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK | 4 | ns | |
tsu(CRS_DV-REF_CLK) | Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK | 4 | ns | ||
tsu(RX_ER-REF_CLK) | Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK | 4 | ns | ||
RMII5 | th(REF_CLK-RXD) | Hold time RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK | 2 | ns | |
th(REF_CLK-CRS_DV) | Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK | 2 | ns | ||
th(REF_CLK-RX_ER) | Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK | 2 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
RMII6 | td(REF_CLK-TXD) | Delay time, RMII[x]_REF_CLK High to RMII[x]_ TXD[1:0] valid | 2 | 10 | ns |
td(REF_CLK-TX_EN) | Delay time, RMII[x]_REF_CLK to RMII[x]_TX_EN valid | 2 | 10 | ns |