SLVS568E January   2005  – July 2025 TLV341 , TLV341A , TLV342 , TLV342S

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information: TLV341
    5. 5.5  Thermal Information: TLV342
    6. 5.6  Thermal Information: TLV342S
    7. 5.7  Electrical Characteristics: V+ = 1.8V
    8. 5.8  Electrical Characteristics: V+ = 5V
    9. 5.9  Shutdown Characteristics: V+ = 1.8V
    10. 5.10 Shutdown Characteristics: V+ = 5V
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 PMOS Input Stage
      2. 6.3.2 CMOS Output Stage
      3. 6.3.3 Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Electrical Characteristics: V+ = 1.8V

V+ = 1.8V, GND = 0V, VIC = VO = V+/2, RL > 1MΩ (unless otherwise noted). See Section 5.9.
PARAMETER TEST CONDITIONS TA MIN TYP(1) MAX UNIT
VIO Input offset voltage Standard grade 25°C 0.3 4 mV
Full range 4.5
A grade 25°C 0.3 1.25
0°C to 125°C 0.3 1.5
–40°C to 125°C 0.3 1.7
αVIO Average temperature coefficient of input offset voltage Full range 1.9 μV/°C
IIB Input bias current 25°C 1 100 pA
–40°C to 85°C 375
–40°C to 125°C 3000
IIO Input offset current 25°C 6.6 fA
CMRR Common-mode rejection ratio 0 ≤ VICR ≤ 1.2V 25°C 60 85 dB
Full range 50
kSVR Supply-voltage rejection ratio 1.8V ≤ V+ ≤ 5V 25°C 75 95 dB
Full range 65
VICR Common-mode input voltage range CMRR ≥ 60dB 25°C 0 1.2 V
AV Large-signal voltage gain(2) RL = 10kΩ to 1.35V 25°C 70 110 dB
Full range 60
RL = 2kΩ to 1.35V 25°C 65 100
Full range 55
VO Output swing
(delta from supply rails)		 RL = 2kΩ to 1.35V Low level 25°C 22 50 mV
Full range 75
High level 25°C 25 50
Full range 75
RL = 10kΩ to 1.35V Low level 25°C 14 20
Full range 25
High level 25°C 7 20
Full range 25
ICC Supply current (per channel) 25°C 150 200 μA
Full range 210
IOS Output short-circuit current Sourcing 25°C 6 12 mA
Sinking 10 20
SR Slew rate RL = 10kΩ(3) 25°C 0.9 V/μs
GBW Unity-gain bandwidth RL = 10kΩ, CL = 200pF 25°C 2.2 MHz
φm Phase margin RL = 100kΩ, CL = 200pF 25°C 55 °
Gm Gain margin RL = 100kΩ, CL = 200pF 25°C 15 dB
Vn Equivalent input noise voltage f = 1kHz 25°C 33 nV/√ Hz
In Equivalent input noise current f = 1kHz 25°C 0.001 pA/√ Hz
THD Total harmonic distortion f = 1kHz, AV = 1, RL = 600Ω,
VI = 1 VPP		 25°C 0.015%
(1) Typical values represent the most likely parametric norm.
(2) GND + 0.2V ≤ VO ≤ V+ – 0.2V
(3) Connected as voltage follower with 2VPP step input. Number specified is the slower of the positive and negative slew rates.