SLVSET9F September   2018  – February 2023 TPS1663

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Hot Plug-In and In-Rush Current Control
        1. 9.3.1.1 Thermal Regulation Loop
      2. 9.3.2  Undervoltage Lockout (UVLO)
      3. 9.3.3  Overvoltage Protection (OVP)
      4. 9.3.4  Overload and Short Circuit Protection
        1. 9.3.4.1 Overload Protection
        2. 9.3.4.2 Short Circuit Protection
          1. 9.3.4.2.1 Start-Up With Short-Circuit On Output
      5. 9.3.5  Output Power Limiting, PLIM (TPS16632 Only)
      6. 9.3.6  Current Monitoring Output (IMON)
      7. 9.3.7  FAULT Response (FLT)
      8. 9.3.8  Power Good Output (PGOOD)
      9. 9.3.9  IN, P_IN, OUT and GND Pins
      10. 9.3.10 Thermal Shutdown
      11. 9.3.11 Low Current Shutdown Control (SHDN)
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Programming the Current-Limit Threshold R(ILIM) Selection
        2. 10.2.2.2 Undervoltage Lockout and Overvoltage Set Point
        3. 10.2.2.3 Setting Output Voltage Ramp Time (tdVdT)
          1. 10.2.2.3.1 Support Component Selections RPGOOD and C(IN)
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Simple 24-V Power Supply Path Protection
    4. 10.4 Power Supply Recommendations
      1. 10.4.1 Transient Protection
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RGE|24
  • PWP|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Timing Requirements

–40°C ≤ TA = TJ ≤ +125°C, 4.5 V < V(IN) = V(P_IN) < 60 V, V( SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD =  FLT = OPEN, C(OUT) = 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))
PARAMETERTEST CONDITIONSMINNOMMAXUNIT
UVLO INPUT (UVLO)
UVLO_ton(dly)UVLO switch turnon delayUVLO↑ (100 mV above V(UVLOR)) to V(OUT) = 100 mV, C(dVdT) ≥ 10 nF,  [C(dVdT) in nF]742 + 49.5 x C(dVdT)µs
UVLO_toff(dly)UVLO switch turnoff delayUVLO↓(20 mV below V(UVLOF)) to FLT↓91116µs
tUVLO_FLT(dly)UVLO to Fault de-assertion delayUVLO↑  to FLT ↑ delay500617700µs
OVER VOLTAGE PROTECTION INPUT (OVP)
OVP_toff(dly)OVP switch turnOFF delayOVP↑ (20 mV above V(OVPR)) to FLT↓8.51114µs
OVP_ton(dly)OVP switch disable delayOVP↓ (100 mV below V(OVPF)) to FET ON ,  C(dVdT) ≥ 10 nF, [C(dVdT) in nF]150 + 49.5 x C(dVdT)µs
tOVC(dly)Maximum duration in over voltage clamp operationTPS16632 only162ms
OVC_tFLT(dly)FLT assertion delay in over voltage clamp operationTPS16632 only617µs
SHUTDOWN CONTROL INPUT ( SHDN)
tSD(dly)SHUTDOWN entry delaySHDN↓ (below V(SHUTF)) to FET OFF0.811.5µs
CURRENT LIMIT
tFASTTRIP(dly)Hot-short response timeI(OUT) > I(SCP)1µs
Soft short responseI(FASTTRIP) < I(OUT) < I(SCP)2.23.24.5µs
tCL_PLIM(dly)Maximum duration in current & (power limiting: TPS16632 Only)129162202ms
tCL_PLIM_FLT(dly)FLT delay in current & (power limiting: TPS16632 Only)1.091.31.6ms
OUTPUT RAMP CONTROL (dVdT)
t(FASTCHARGE)Output ramp time in fast chargingC(dVdT) = Open, 10% to 90% V(OUT), C(OUT) = 1 µF; V(IN) = 24V350495700µs
t(dVdT)Output ramp timeC(dVdT) = 22 nF, 10% to 90% V(OUT), V(IN) = 24 V8.35ms
POWER GOOD (PGOOD)
tPGOODRPGOOD delay (deglitch) timeRising edge811.513ms
tPGOODFPGOOD delay (deglitch) timeFalling edge81013ms
THERMAL PROTECTION
t(TSD_retry)Retry delay in TSDMODE = GND500648800ms
t(Treg_timeout)Thermal Regulation Timeout1.11.251.5s