SWCS133D September 2015 – May 2019 TPS65094
PRODUCTION DATA.
Programmable Power Good delay for PCH_PWROK pin, measured from the moment when all VRs reach the regulation range to Power Good assertion.
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Bit Name | RESERVED | RESERVED | RESERVED | RESERVED | RESERVED | PWROKDELAY
[2] |
PWROKDELAY
[1] |
PWROKDELAY
[0] |
TPS65094x | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
Access | R | R | R | R | R | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
2–0 | PWROKDELAY[2:0] | R/W | 111 | Programmable delay measured from the moment all rails have reached regulation voltage to assertion of PCH_PWROK. All values have ±10% variation.
000 = 2.5 ms 001 = 5.0 ms 010 = 10 ms 011 = 15 ms 100 = 20 ms 101 = 50 ms 110 = 75 ms 111 = 100 ms (default) |