This resource has two modes:
VRTC supplies the digital part of TPS65903x-Q1 devices. In the BACKUP state, the VRTC regulator is in low-power mode and the digital activity is reduced to the RTC parts only and maintained in retention registers of the backup domain. The rest of the digital is under reset and the clocks are gated. In the OFF state, the turn-on events and detection mechanism are also added to the previous RTC current load. In the BACKUP and OFF states, the external load on VRTC should not exceed 0.5 mA. In the ACTIVE state, VRTC switches automatically into ACTIVE mode. The reset is released and the clocks are available. In SLEEP state, VRTC is kept active. The reset is released and only the 32-kHz clock is available. To reduce power consumption, low-power mode can be selected by software.
For silicon revision 1.3 or earlier, if VCC is discharged rapidly and then resupplied, a POR may not be reliably generated. In this case a pulldown resistor can be added on the LDOVRTC output. See Section 6.4.11 for details. See Section 6.3.10 to identify the silicon version in the device.