The total start-up time of TPS65903x-Q1 from the first supply insertion until the release of reset to the processor is defined by the boot time of internal resources as well as the OTP defined boot sequence.
Following figure shows the power up sequence timing and the generation of the RESET_OUT signal.
The t1 time is the delay between VCC1 crossing the POR threshold and VIO (First rail in the power sequence) rising up. The t1 time must be at least 6 ms. If the time from VCC to VIO is less than 6 ms, the VIO buffers are supplied while the OTP is still being initialized, which could cause glitches on any VIO output buffer. Supplying VIO at least 6 ms after supplying VCC makes sure that the OTP is initialized and the output buffers are held low when VIO is supplied. The VIO_IN pin may be supplied before or after the first rail in the power sequence is enabled, as long as it is at least 6 ms after VCC.
The t2 time is the internal 16.384-MHz crystal oscillator start-up time, or the external 32kHz clock input availability delay time.
The t3 time is the delay between the power up sequence start and RESET_OUT release. RESET_OUT will be released once power up sequence is complete and:
The duration of the power up sequence depends on OTP programming; average value is about 10ms.