6.4.7 Reset Levels
The device series resource control registers are defined by three categories:
- POR registers: POR registers
- HW registers: HARDWARE registers
- SWO registers: SWITCHOFF registers
These registers are associated to three levels of reset as described below:
- Power-on reset (POR)
- Power-on reset happens when the device gets its supplies and transition from the NOSUPPLY state to the BACKUP state. This is the global device reset.
- Additionally, SMPS_THERMAL_STATUS, SMPS_SHORT_STATUS, SMSP_POWERGOOD_MASK, LDO_SHORT_STATUS and SWOFF_STATUS registers are in POR domain. This list is indicative only.
- HWRST – Hardware reset
- Hardware reset happens when any OFF request is configured to generate a hardware reset. This reset triggers a transition to the OFF state from either the ACTIVE or SLEEP state (execute either the ACT2OFF or SLP2OFF sequence).
- SWORST – Switch-off reset
- Switch-off reset happens when any OFF request is configured to not generate a hardware reset. This reset acts as the HWRST, except only the SWO registers are reset. The device goes in the OFF state, from either ACTIVE or SLEEP, and therefore executes the ACT2OFF or SLP2OFF sequence.
- Power resource control registers for SMPS and LDO voltage levels and operating mode control are in SWORST domain. Additionally some registers control the 32-kHz, REGENx and SYSENx, watchdog, external charger control, and VSYS_MON comparator. This list is indicative only.
Table 6-15 lists the reset levels, and Figure 6-25 shows the reset levels versus registers.
Table 6-15 Reset Levels
||POR, HW, SWO
||This reset level is the lowest level, for which all registers are reset.
||During hardware reset (HWRST), all registers are reset except the POR registers.
||Only the SWO registers are reset.
|Figure 6-25 Reset Levels versus Registers