The TPS65903x-Q1 device contains a SYNCDCDC input to sync DC-DCs with the external clock.
In forced PWM mode, SMPSs are synchronized on an external input clock (SYNCDCDC) whereas in ECO-mode, or if the SYNCDCDC pin is grounded, the switching frequency is based on an internal RC oscillator. The clock generated from the internal RC oscillator can be output through GPIO5 to provide synchronization clock to external SMPSs. For PWM mode, a PLL is present to buffer the external input clock to create nine clock signals for the nine SMPSs with different phases.
The sync clock dither specification parameters are based on a triangular dither pattern, but other patterns that comply with the minimum and maximum sync frequency range and the maximum dither slope can also be used.
The ollowing figure shows ƒSYNC, the frequency of SYNCDCDC input clock and ƒS, the frequency of PLL output signal.
When there is no clock present on SYNCDCDC ball, the PLL generates a clock with a frequency equal to ƒFALLBACK.
If a clock is present on SYNCDCDC ball with a frequency between ƒSAT,LO and ƒSAT,HI, then the PLL is synchronised on SYNCDCDC clock and generates a clock with frequency equal to fSYNC.
If ƒSYNC is higher than ƒSAT,HI, then the PLL generates a clock with a frequency equal to ƒSAT,HI.
If fSYNC is smaller than ƒSAT,LO, then the PLL generates a clock with a frequency equal to ƒSAT,LO.