SLUSD66D September 2019 – February 2021 TPS92520-Q1
PRODUCTION DATA
The device is powered by an external 5-V supply connected to V5D and V5A pins. Operation is enabled when V5D and V5A exceed the 4.1-V (typ) rising threshold and is disabled when either V5D or V5A drops below the 4-V (typ) falling threshold. The comparator provides 100-mV of hysteresis to avoid chatter during transitions. The V5D supply powers the internal digital logic, a 10.8-MHz oscillator, and the high-side and low-side gate driver circuits. The V5A supply powers the analog-to-digital converter (ADC), the digital-to-analog converters (DACs), and the sensitive analog circuits. The two bias pins can be connected together on the PCB or through a series 10-Ω resistor between V5D and V5A with 5-V external supply connected directly to the V5D pin. TI recommends a capacitor from each pin to GND . The recommended range for the bypass capacitor from V5D pin to ground is between 1 µF and 4.7 µF. The recommended range from the V5A pin to ground is between 100 nF and 1 µF. The bypass capacitor from V5D to GND must be 10 times larger than the bootstrap capacitor, CBST, to support proper operation during PWM dimming. The voltage on V5D and V5A must never exceed 5.5 V.
The power cycle (PC) bit indicates a fault condition when both V5D and V5A are below the 4 V. At power up, the PC bit is set and must be cleared before enabling the operation of individual channels. Reading the STATUS3 register clears the PC bit.
In device sleep state, the V5A input is internally disconnected to reduce power consumption. As the internal voltage drops below the 4-V threshold, the V5AUV bit is set in the STATUS3 register to indicate bias undervoltage condition. The fault clears when the device is programmed to exit the sleep state and assumes normal operation. See the Device Functional Modes section for more details.