SLUSEJ1 December   2021 TPSM8D6C24

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Average Current-Mode Control
        1. 7.3.1.1 On-Time Modulator
        2. 7.3.1.2 Current Error Integrator
        3. 7.3.1.3 Voltage Error Integrator
      2. 7.3.2  Linear Regulators
      3. 7.3.3  AVIN and PVIN Pins
      4. 7.3.4  Input Undervoltage Lockout (UVLO)
        1. 7.3.4.1 Fixed AVIN UVLO
        2. 7.3.4.2 Fixed VDD5 UVLO
        3. 7.3.4.3 Programmable PVIN UVLO
        4. 7.3.4.4 EN/UVLO Pin
      5. 7.3.5  Start-Up and Shutdown
      6. 7.3.6  Differential Sense Amplifier and Feedback Divider
      7. 7.3.7  Set Output Voltage and Adaptive Voltage Scaling (AVS)
        1. 7.3.7.1 Reset Output Voltage
        2. 7.3.7.2 Soft Start
      8. 7.3.8  Prebiased Output Start-Up
      9. 7.3.9  Soft Stop and (65h) TOFF_FALL Command
      10. 7.3.10 Power Good (PGOOD)
      11. 7.3.11 Set Switching Frequency
      12. 7.3.12 Frequency Synchronization
      13. 7.3.13 Loop Follower Detection
      14. 7.3.14 Current Sensing and Sharing
      15. 7.3.15 Telemetry
      16. 7.3.16 Overcurrent Protection
      17. 7.3.17 Overvoltage/Undervoltage Protection
      18. 7.3.18 Overtemperature Management
      19. 7.3.19 Fault Management
      20. 7.3.20 Back-Channel Communication
      21. 7.3.21 Switching Node (SW)
      22. 7.3.22 PMBus General Description
      23. 7.3.23 PMBus Address
      24. 7.3.24 PMBus Connections
    4. 7.4 Device Functional Modes
      1. 7.4.1 Programming Mode
      2. 7.4.2 Standalone/Loop Controller/Loop Follower Mode Pin Connections
      3. 7.4.3 Continuous Conduction Mode
      4. 7.4.4 Operation With CNTL Signal (EN/UVLO)
      5. 7.4.5 Operation with (01h) OPERATION Control
      6. 7.4.6 Operation with CNTL and (01h) OPERATION Control
    5. 7.5 Programming
      1. 7.5.1 Supported PMBus Commands
      2. 7.5.2 Pin Strapping
        1. 7.5.2.1 Programming MSEL1
        2. 7.5.2.2 Programming MSEL2
        3. 7.5.2.3 Programming VSEL
        4. 7.5.2.4 Programming ADRSEL
        5. 7.5.2.5 Programming MSEL2 for a Loop Follower Device (GOSNS Tied to BP1V5)
        6. 7.5.2.6 Pin-Strapping Resistor Configuration
    6. 7.6 Register Maps
      1. 7.6.1  Conventions for Documenting Block Commands
      2. 7.6.2  (01h) OPERATION
      3. 7.6.3  (02h) ON_OFF_CONFIG
      4. 7.6.4  (03h) CLEAR_FAULTS
      5. 7.6.5  (04h) PHASE
      6. 7.6.6  (10h) WRITE_PROTECT
      7. 7.6.7  (15h) STORE_USER_ALL
      8. 7.6.8  (16h) RESTORE_USER_ALL
      9. 7.6.9  (19h) CAPABILITY
      10. 7.6.10 (1Bh) SMBALERT_MASK
      11. 7.6.11 (1Bh) SMBALERT_MASK_VOUT
      12. 7.6.12 (1Bh) SMBALERT_MASK_IOUT
      13. 7.6.13 (1Bh) SMBALERT_MASK_INPUT
      14. 7.6.14 (1Bh) SMBALERT_MASK_TEMPERATURE
      15. 7.6.15 (1Bh) SMBALERT_MASK_CML
      16. 7.6.16 (1Bh) SMBALERT_MASK_OTHER
      17. 7.6.17 (1Bh) SMBALERT_MASK_MFR
      18. 7.6.18 (20h) VOUT_MODE
      19. 7.6.19 (21h) VOUT_COMMAND
      20. 7.6.20 (22h) VOUT_TRIM
      21. 7.6.21 (24h) VOUT_MAX
      22. 7.6.22 (25h) VOUT_MARGIN_HIGH
      23. 7.6.23 (26h) VOUT_MARGIN_LOW
      24. 7.6.24 (27h) VOUT_TRANSITION_RATE
      25. 7.6.25 (29h) VOUT_SCALE_LOOP
      26. 7.6.26 (2Bh) VOUT_MIN
      27. 7.6.27 (33h) FREQUENCY_SWITCH
      28. 7.6.28 (35h) VIN_ON
      29. 7.6.29 (36h) VIN_OFF
      30. 7.6.30 (37h) INTERLEAVE
      31. 7.6.31 (38h) IOUT_CAL_GAIN
      32. 7.6.32 (39h) IOUT_CAL_OFFSET
      33. 7.6.33 (40h) VOUT_OV_FAULT_LIMIT
      34. 7.6.34 (41h) VOUT_OV_FAULT_RESPONSE
      35. 7.6.35 (42h) VOUT_OV_WARN_LIMIT
      36. 7.6.36 (43h) VOUT_UV_WARN_LIMIT
      37. 7.6.37 (44h) VOUT_UV_FAULT_LIMIT
      38. 7.6.38 (45h) VOUT_UV_FAULT_RESPONSE
      39. 7.6.39 (46h) IOUT_OC_FAULT_LIMIT
      40. 7.6.40 (47h) IOUT_OC_FAULT_RESPONSE
      41. 7.6.41 (4Ah) IOUT_OC_WARN_LIMIT
      42. 7.6.42 (4Fh) OT_FAULT_LIMIT
      43. 7.6.43 (50h) OT_FAULT_RESPONSE
      44. 7.6.44 (51h) OT_WARN_LIMIT
      45. 7.6.45 (55h) VIN_OV_FAULT_LIMIT
      46. 7.6.46 (56h) VIN_OV_FAULT_RESPONSE
      47. 7.6.47 (58h) VIN_UV_WARN_LIMIT
      48. 7.6.48 (60h) TON_DELAY
      49. 7.6.49 (61h) TON_RISE
      50. 7.6.50 (62h) TON_MAX_FAULT_LIMIT
      51. 7.6.51 (63h) TON_MAX_FAULT_RESPONSE
      52. 7.6.52 (64h) TOFF_DELAY
      53. 7.6.53 (65h) TOFF_FALL
      54. 7.6.54 (78h) STATUS_BYTE
      55. 7.6.55 (79h) STATUS_WORD
      56. 7.6.56 (7Ah) STATUS_VOUT
      57. 7.6.57 (7Bh) STATUS_IOUT
      58. 7.6.58 (7Ch) STATUS_INPUT
      59. 7.6.59 (7Dh) STATUS_TEMPERATURE
      60. 7.6.60 (7Eh) STATUS_CML
      61. 7.6.61 (7Fh) STATUS_OTHER
      62. 7.6.62 (80h) STATUS_MFR_SPECIFIC
      63. 7.6.63 (88h) READ_VIN
      64. 7.6.64 (8Bh) READ_VOUT
      65. 7.6.65 (8Ch) READ_IOUT
      66. 7.6.66 (8Dh) READ_TEMPERATURE_1
      67. 7.6.67 (98h) PMBUS_REVISION
      68. 7.6.68 (99h) MFR_ID
      69. 7.6.69 (9Ah) MFR_MODEL
      70. 7.6.70 (9Bh) MFR_REVISION
      71. 7.6.71 (9Eh) MFR_SERIAL
      72. 7.6.72 (ADh) IC_DEVICE_ID
      73. 7.6.73 (AEh) IC_DEVICE_REV
      74. 7.6.74 (B1h) USER_DATA_01 (COMPENSATION_CONFIG)
      75. 7.6.75 (B5h) USER_DATA_05 (POWER_STAGE_CONFIG)
      76. 7.6.76 (D0h) MFR_SPECIFIC_00 (TELEMETRY_CONFIG)
      77. 7.6.77 (DAh) MFR_SPECIFIC_10 (READ_ALL)
      78. 7.6.78 (DBh) MFR_SPECIFIC_11 (STATUS_ALL)
      79. 7.6.79 (DCh) MFR_SPECIFIC_12 (STATUS_PHASE)
      80. 7.6.80 (E4h) MFR_SPECIFIC_20 (SYNC_CONFIG)
      81. 7.6.81 (ECh) MFR_SPECIFIC_28 (STACK_CONFIG)
      82. 7.6.82 (EDh) MFR_SPECIFIC_29 (MISC_OPTIONS)
      83. 7.6.83 (EEh) MFR_SPECIFIC_30 (PIN_DETECT_OVERRIDE)
      84. 7.6.84 (EFh) MFR_SPECIFIC_31 (Loop Follower_ADDRESS)
      85. 7.6.85 (F0h) MFR_SPECIFIC_32 (NVM_CHECKSUM)
      86. 7.6.86 (F1h) MFR_SPECIFIC_33 (SIMULATE_FAULT)
      87. 7.6.87 (FCh) MFR_SPECIFIC_44 (FUSION_ID0)
      88. 7.6.88 (FDh) MFR_SPECIFIC_45 (FUSION_ID1)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design With WEBENCH® Tools
        2. 8.2.2.2  Switching Frequency
        3. 8.2.2.3  Output Voltage Setting (VSEL Pin)
        4. 8.2.2.4  Compensation Selection (MSEL1 Pin)
        5. 8.2.2.5  Output Capacitor Selection
          1. 8.2.2.5.1 Output Voltage Ripple
        6. 8.2.2.6  Input Capacitor Selection
        7. 8.2.2.7  Soft Start, Overcurrent Protection, and Stacking Configuration (MSEL2 Pin)
        8. 8.2.2.8  Enable and UVLO
        9. 8.2.2.9  ADRSEL
        10. 8.2.2.10 BCX_CLK and BCX_DAT
      3. 8.2.3 Application Curves
      4. 8.2.4 Two-Phase Application
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Two-Phase Detailed Design Procedure
          1. 8.2.4.2.1  Switching Frequency
          2. 8.2.4.2.2  Output Voltage Setting (VSEL Pin)
          3. 8.2.4.2.3  Compensation Selection (MSEL1 Pin)
          4. 8.2.4.2.4  Output Capacitor Selection
          5. 8.2.4.2.5  Input Capacitor Selection
          6. 8.2.4.2.6  GOSNS/Loop Follower Pin of Loop Follower Devices
          7. 8.2.4.2.7  Soft Start, Overcurrent Protection, and Stacking Configuration (MSEL2 Pin)
          8. 8.2.4.2.8  Enable, UVLO
          9. 8.2.4.2.9  VSHARE Pin
            1. 8.2.4.2.9.1 ADRSEL Pin
          10. 8.2.4.2.10 SYNC Pin
          11. 8.2.4.2.11 VOSNS Pin of Loop Follower Devices
          12. 8.2.4.2.12 Unused Pins of Loop Follower Devices
        3. 8.2.4.3 Two-Phase Application Curves
      5. 8.2.5 Four-Phase Application
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Performance on the TI EVM
      2. 10.2.2 EMI
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Texas Instruments Fusion Digital Power Designer
        2. 11.1.2.2 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • MOW|59
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Fault Management

For the response on OC fault, OT fault, and thermal shutdown for multi-phase stack, the shutdown response has the highest priority, followed by restart response. Continue operating without interruption response has the lowest priority.

When multiple faults occur in rapid succession, it is possible for the first fault to occur to mask the second fault. If the first fault to be detected is configured to continue operating without interruption, and the second fault is configured to shutdown and restart, the second fault will shutdown but can fail to restart as programmed.

Table 7-4 Fault Protection Summary
FAULT OR WARNINGPROGRAMMINGFAULT RESPONSE SETTINGFET BEHAVIORACTIVE DURING tON_RISESMB_ALRTMASKABLEPGOOD LOGIC
Internal OT faultSection 7.6.42ShutdownBoth FETs offYesYYLow
RestartBoth FETs off, restart
IgnoreFETS still controlled by PWMHigh
Internal OT warningSection 7.6.44Shutdown or restart on FaultFETS still controlled by PWMYesYYHigh
Ignore fault
TSDThreshold fixed internallyShutdownBoth FETs offYesYYLow
RestartBoth FETs off, restart
IgnoreFETS still controlled by PWM
High
Low Side OC faultSection 7.6.39Shutdown3 PWM counts, then both FETs offYesYYLow
Restart3 PWM counts, then both FETs off, restart after [DELAY] × tON_RISE
IgnoreFETS still controlled by PWMHigh
Low Side OC warningSection 7.6.41Shutdown or restart on FaultFETS still controlled by PWMYesYYHigh
Ignore fault
Negative OC fault (lower priority than OVF)N/AEnableTurn off LS FETYesYYLow
DisableFETS still controlled by PWMHigh
High side OC faultSection 7.6.39ShutdownThree cycles of pulse-by-pulse current limiting followed by both FETs offYesYYLow
Restart3 cycles of pulse-by-pulse current limiting followed by both FETs off, restart after [DELAY] × tON_RISE
IgnoreFETS still controlled by PWMHigh
Vout OV faultSection 7.6.33ShutdownLS FET latched ON or turned on till VOUTreaches 200 mV/VOUT_SCALE_LOOP; HS FET OFFNoYYLow
RestartLS FET latched ON or turned on till VOUTreaches 200 mV/VOUT_SCALE_LOOP; HS FET OFF, restart after [DELAY] × tON_RISE
IgnoreFETS still controlled by PWMHigh
VOUT OVF fixSection 7.6.33ShutdownLS FET latched ON or turned on till VOUTreaches 200 mV/VOUT_SCALE_LOOP; HS FET OFFYesYYLow
RestartLS FET latched ON or turned on till VOUTreaches 200 mV/VOUT_SCALE_LOOP; HS FET OFF, restart after [DELAY] × tON_RISE
IgnoreFETS still controlled by PWMHigh
Vout OV warningSection 7.6.35Shutdown or restart on FaultFETS still controlled by PWMNoYYHigh
Ignore fault
Vout UV faultSection 7.6.37ShutdownBoth FETs offNoYYLow
RestartBoth FETs off, restart after [DELAY] × tON_RISE
IgnoreFETS still controlled by PWMHigh
Vout UV warningSection 7.6.36Shutdown or restart on FaultFETS still controlled by PWMNoYYLow
Ignore fault
tON MAX raultSection 7.6.50ShutdownBoth FETs offYesYYLow
RestartBoth FETs off, restart after [DELAY] × tON_RISE
IgnoreFETS still controlled by PWMHigh
PVin UVLOSection 7.6.28, Section 7.6.29ShutdownBoth FETs offYesYYLow
PVIN OV FAULTSection 7.6.45ShutdownBoth FETs offYesYYLow
RestartBoth FETs off, restart
IgnoreFETS still controlled by PWMHigh
BCX_faultN/AN/AFETS still controlled by PWMYesYYHigh
Pin_Strap_NonConvergeN/AVSELBoth FETs off, pull low VSHARENo (active before tON_RISE)NN/ALow
MSEL1
MSEL2
ADRSEL
SYNC_FaultN/ALoop controller or standalone deviceFETS still controlled by PWMYesNN/AHigh
Loop follower deviceBoth FETs off, pull low VSHARE
Low
SYNC_High/LowN/ALoop controller or standalone deviceFETS still controlled by PWMYesNN/AHigh
Loop follower deviceBoth FETs off, pull low VSHARE
Low