SLOSEG3 October   2025 TRF1305A2

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - AC Specifications in D2D Configuration
    6. 6.6 Electrical Characteristics - AC Specifications in S2D Configuration
    7. 6.7 Electrical Characteristics - DC and Timing Specifications
    8. 6.8 Typical Characteristics: D2D Configuration
    9. 6.9 Typical Characteristics: S2D Configuration
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Differential RF Amplifier
      2. 7.3.2 Output Common-Mode Control
      3. 7.3.3 Internal Resistor Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
        1. 7.4.1.1 Input Common-Mode Extension
      2. 7.4.2 Power-Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Interface Considerations
        1. 8.1.1.1 Single-Ended Input
        2. 8.1.1.2 Differential Input
        3. 8.1.1.3 DC-Coupling Considerations
      2. 8.1.2 Gain Adjustment With External Resistors in a Differential Input Configuration
    2. 8.2 Typical Application
      1. 8.2.1 TRF1305A2 as ADC Driver in a Zero-IF Receiver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Supply Voltages
      2. 8.3.2 Single-Supply Operation
      3. 8.3.3 Split-Supply Operation
      4. 8.3.4 Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RYP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.8 Typical Characteristics: D2D Configuration

at TA = 25℃, VS+ = 5V, VS– = 0V, floating VOCM, PD, and MODE pins, VICM = mid-supply, D2D ac-coupled input/output configuration with ZS = 100Ω, ZL = 100Ω, external input resistor network (see Figure 8-6), inputs de-embedded up to RIN_SH and outputs up to the device pins, ambient temperatures shown, and resistor network included as part of DUT characteristic plots (unless otherwise noted)

TRF1305A2 Power Gain (Sdd21) Across Temperature
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-1 Power Gain (Sdd21) Across Temperature
TRF1305A2 Input Return Loss (Sdd11) Across Temperature
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-3 Input Return Loss (Sdd11) Across Temperature
TRF1305A2 Output Return Loss (Sdd22) Across Temperature
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-5 Output Return Loss (Sdd22) Across Temperature
TRF1305A2 Reverse Isolation (Sdd12) Across Temperature
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-7 Reverse Isolation (Sdd12) Across Temperature
TRF1305A2 OIP3 Across Temperature
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-9 OIP3 Across Temperature
TRF1305A2 OIP3 Across Temperature
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-11 OIP3 Across Temperature
TRF1305A2 IMD3 Lower Across Temperature
At (2f1 – f2) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-13 IMD3 Lower Across Temperature
TRF1305A2 IMD3 Higher Across Temperature
At (2f2 – f1) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-15 IMD3 Higher Across Temperature
TRF1305A2 IMD3 Lower Across Temperature
At (2f1 – f2) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-17 IMD3 Lower Across Temperature
TRF1305A2 IMD3 Higher Across Temperature
At (2f2 – f1) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-19 IMD3 Higher Across Temperature
TRF1305A2 OIP2 Across Temperature
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-21 OIP2 Across Temperature
TRF1305A2 OIP2 Across Temperature
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-23 OIP2 Across Temperature
TRF1305A2 IMD2 Lower Across Temperature
At (f2 – f1) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-25 IMD2 Lower Across Temperature
TRF1305A2 IMD2 Higher Across Temperature
At (f1 + f2) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-27 IMD2 Higher Across Temperature
TRF1305A2 IMD2 Lower Across Temperature
At (f2 – f1) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-29 IMD2 Lower Across Temperature
TRF1305A2 IMD2 Higher Across Temperature
At (f1 + f2) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-31 IMD2 Higher Across Temperature
TRF1305A2 HD2 Across Temperature
PO = 7dBm
Figure 6-33 HD2 Across Temperature
TRF1305A2 HD2 Across Temperature
PO = 1dBm
Figure 6-35 HD2 Across Temperature
TRF1305A2 HD3 Across Temperature
PO = 7dBm
Figure 6-37 HD3 Across Temperature
TRF1305A2 HD3 Across Temperature
PO = 1dBm
Figure 6-39 HD3 Across Temperature
TRF1305A2 OP1dB Across Temperature
 
Figure 6-41 OP1dB Across Temperature
TRF1305A2 Noise Figure Across Temperature
 
Figure 6-43 Noise Figure Across Temperature
TRF1305A2 OIP3 Across VICM and VOCM at 500MHz, Ch1
PO = 1dBm/tone, 2MHz tone spacing, dc-coupled inputs with VICM forced through bias tees
Figure 6-45 OIP3 Across VICM and VOCM at 500MHz, Ch1
TRF1305A2 OIP3 Across VICM and VOCM at 2GHz, Ch1
PO = 1dBm/tone, 2MHz tone spacing, dc-coupled inputs with VICM forced through bias tees
Figure 6-47 OIP3 Across VICM and VOCM at 2GHz, Ch1
TRF1305A2 OIP2 Across VICM and VOCM at 500MHz, Ch1
PO = 1dBm/tone, 2MHz tone spacing, dc-coupled inputs with VICM forced through bias tees
Figure 6-49 OIP2 Across VICM and VOCM at 500MHz, Ch1
TRF1305A2 OIP2 Across VICM and VOCM at 2GHz, Ch1
PO = 1dBm/tone, 2MHz tone spacing, dc-coupled inputs with VICM forced through bias tees
Figure 6-51 OIP2 Across VICM and VOCM at 2GHz, Ch1
TRF1305A2 OP1dB Across VICM and VOCM at 500MHz, Ch1
dc-coupled inputs with VICM forced through bias tees
Figure 6-53 OP1dB Across VICM and VOCM at 500MHz, Ch1
TRF1305A2 OP1dB Across VICM and VOCM at 2GHz, Ch1
dc-coupled inputs with VICM forced through bias tees
Figure 6-55 OP1dB Across VICM and VOCM at 2GHz, Ch1
TRF1305A2 HD2 Across VICM and VOCM at 500MHz, Ch1
PO = 7dBm, dc-coupled inputs with
VICM forced through bias tees
Figure 6-57 HD2 Across VICM and VOCM at 500MHz, Ch1
TRF1305A2 HD2 Across VICM and VOCM at 2GHz, Ch1
PO = 7dBm, dc-coupled inputs with
VICM forced through bias tees
Figure 6-59 HD2 Across VICM and VOCM at 2GHz, Ch1
TRF1305A2 HD3 Across VICM and VOCM at 500MHz, Ch1
PO = 7dBm, dc-coupled inputs with
VICM forced through bias tees
Figure 6-61 HD3 Across VICM and VOCM at 500MHz, Ch1
TRF1305A2 HD3 Across VICM and VOCM at 2GHz, Ch1
PO = 7dBm, dc-coupled inputs with
VICM forced through bias tees
Figure 6-63 HD3 Across VICM and VOCM at 2GHz, Ch1
TRF1305A2 Step Response
DC-coupled, VS+ = 2.5V, VS– = –2.5V
Figure 6-65 Step Response
TRF1305A2 Differential Output Power Across Differential Input Power, Ch1
 
Figure 6-67 Differential Output Power Across Differential Input Power, Ch1
TRF1305A2 Common-Mode Rejection Ratio (CMRR)
PIN = –20dBm at each driven input pin with 50Ω source, c in Sdc21 and Scc21 is for common-mode
Figure 6-69 Common-Mode Rejection Ratio (CMRR)
TRF1305A2 Overdrive Recovery Response, Ch1
DC-coupled, VS+ = 2.5V, VS– = –2.5V, 2 to 5 times output voltages are with an input voltage 2 to 5 times of VIN as shown, respectively
Figure 6-71 Overdrive Recovery Response, Ch1
TRF1305A2 Crosstalk
PIN = –20dBm at each driven input pin with 50Ω source
Figure 6-73 Crosstalk
TRF1305A2 Power Gain (Sdd21) Across Supply Voltage
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-2 Power Gain (Sdd21) Across Supply Voltage
TRF1305A2 Input Return Loss (Sdd11) Across Supply Voltage
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-4 Input Return Loss (Sdd11) Across Supply Voltage
TRF1305A2 Output Return Loss (Sdd22) Across Supply Voltage
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-6 Output Return Loss (Sdd22) Across Supply Voltage
TRF1305A2 Reverse Isolation (Sdd12) Across Supply Voltage
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-8 Reverse Isolation (Sdd12) Across Supply Voltage
TRF1305A2 OIP3 Across Supply Voltage
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-10 OIP3 Across Supply Voltage
TRF1305A2 OIP3 Across Supply Voltage
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-12 OIP3 Across Supply Voltage
TRF1305A2 IMD3 Lower Across Supply Voltage
At (2f1 – f2) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-14 IMD3 Lower Across Supply Voltage
TRF1305A2 IMD3 Higher Across Supply Voltage
At (2f2 – f1) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-16 IMD3 Higher Across Supply Voltage
TRF1305A2 IMD3 Lower Across Supply Voltage
At (2f1 – f2) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-18 IMD3 Lower Across Supply Voltage
TRF1305A2 IMD3 Higher Across Supply Voltage
At (2f2 – f1) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-20 IMD3 Higher Across Supply Voltage
TRF1305A2 OIP2 Across Supply Voltage
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-22 OIP2 Across Supply Voltage
TRF1305A2 OIP2 Across Supply Voltage
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-24 OIP2 Across Supply Voltage
TRF1305A2 IMD2 Lower Across Supply Voltage
At (f2 – f1) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-26 IMD2 Lower Across Supply Voltage
TRF1305A2 IMD2 Higher Across Supply Voltage
At (f1 + f2) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-28 IMD2 Higher Across Supply Voltage
TRF1305A2 IMD2 Lower Across Supply Voltage
At (f2 – f1) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-30 IMD2 Lower Across Supply Voltage
TRF1305A2 IMD2 Higher Across Supply Voltage
At (f1 + f2) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-32 IMD2 Higher Across Supply Voltage
TRF1305A2 HD2 Across Supply Voltage
PO = 7dBm
Figure 6-34 HD2 Across Supply Voltage
TRF1305A2 HD2 Across Supply Voltage
PO = 1dBm
Figure 6-36 HD2 Across Supply Voltage
TRF1305A2 HD3 Across Supply Voltage
PO = 7dBm
Figure 6-38 HD3 Across Supply Voltage
TRF1305A2 HD3 Across Supply Voltage
PO = 1dBm
Figure 6-40 HD3 Across Supply Voltage
TRF1305A2 OP1dB Across Supply Voltage
 
Figure 6-42 OP1dB Across Supply Voltage
TRF1305A2 Noise Figure Across Supply Voltage
 
Figure 6-44 Noise Figure Across Supply Voltage
TRF1305A2 OIP3 Across VICM and VOCM at 500MHz, Ch2
PO = 1dBm/tone, 2MHz tone spacing, dc-coupled inputs with VICM forced through bias tees
Figure 6-46 OIP3 Across VICM and VOCM at 500MHz, Ch2
TRF1305A2 OIP3 Across VICM and VOCM at 2GHz, Ch2
PO = 1dBm/tone, 2MHz tone spacing, dc-coupled inputs with VICM forced through bias tees
Figure 6-48 OIP3 Across VICM and VOCM at 2GHz, Ch2
TRF1305A2 OIP2 Across VICM and VOCM at 500MHz, Ch2
PO = 1dBm/tone, 2MHz tone spacing, dc-coupled inputs with VICM forced through bias tees
Figure 6-50 OIP2 Across VICM and VOCM at 500MHz, Ch2
TRF1305A2 OIP2 Across VICM and VOCM at 2GHz, Ch2
PO = 1dBm/tone, 2MHz tone spacing, dc-coupled inputs with VICM forced through bias tees
Figure 6-52 OIP2 Across VICM and VOCM at 2GHz, Ch2
TRF1305A2 OP1dB Across VICM and VOCM at 500MHz, Ch2
dc-coupled inputs with VICM forced through bias tees
Figure 6-54 OP1dB Across VICM and VOCM at 500MHz, Ch2
TRF1305A2 OP1dB Across VICM and VOCM at 2GHz, Ch2
dc-coupled inputs with VICM forced through bias tees
Figure 6-56 OP1dB Across VICM and VOCM at 2GHz, Ch2
TRF1305A2 HD2 Across VICM and VOCM at 500MHz, Ch2
PO = 7dBm, dc-coupled inputs with
VICM forced through bias tees
Figure 6-58 HD2 Across VICM and VOCM at 500MHz, Ch2
TRF1305A2 HD2 Across VICM and VOCM at 2GHz, Ch2
PO = 7dBm, dc-coupled inputs with
VICM forced through bias tees
Figure 6-60 HD2 Across VICM and VOCM at 2GHz, Ch2
TRF1305A2 HD3 Across VICM and VOCM at 500MHz, Ch2
PO = 7dBm, dc-coupled inputs with
VICM forced through bias tees
Figure 6-62 HD3 Across VICM and VOCM at 500MHz, Ch2
TRF1305A2 HD3 Across VICM and VOCM at 2GHz, Ch2
PO = 7dBm, dc-coupled inputs with
VICM forced through bias tees
Figure 6-64 HD3 Across VICM and VOCM at 2GHz, Ch2
TRF1305A2 Step Response
DC-coupled, VS+ = 2.5V, VS– = –2.5V
Figure 6-66 Step Response
TRF1305A2 Differential Output Power Across Differential Input Power, Ch2
 
Figure 6-68 Differential Output Power Across Differential Input Power, Ch2
TRF1305A2 Gain and Phase Mismatch Between Channels
PIN = –20dBm at each driven input pin with 50Ω source
 
Figure 6-70 Gain and Phase Mismatch Between Channels
TRF1305A2 Overdrive Recovery Response, Ch2
DC-coupled, VS+ = 2.5V, VS– = –2.5V, 2 to 5 times output voltages are with an input voltage 2 to 5 times of VIN as shown, respectively
Figure 6-72 Overdrive Recovery Response, Ch2