SLOSEG3 October   2025 TRF1305A2

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics - AC Specifications in D2D Configuration
    6. 6.6 Electrical Characteristics - AC Specifications in S2D Configuration
    7. 6.7 Electrical Characteristics - DC and Timing Specifications
    8. 6.8 Typical Characteristics: D2D Configuration
    9. 6.9 Typical Characteristics: S2D Configuration
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Fully Differential RF Amplifier
      2. 7.3.2 Output Common-Mode Control
      3. 7.3.3 Internal Resistor Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1 MODE Pin
        1. 7.4.1.1 Input Common-Mode Extension
      2. 7.4.2 Power-Down Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Interface Considerations
        1. 8.1.1.1 Single-Ended Input
        2. 8.1.1.2 Differential Input
        3. 8.1.1.3 DC-Coupling Considerations
      2. 8.1.2 Gain Adjustment With External Resistors in a Differential Input Configuration
    2. 8.2 Typical Application
      1. 8.2.1 TRF1305A2 as ADC Driver in a Zero-IF Receiver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Supply Voltages
      2. 8.3.2 Single-Supply Operation
      3. 8.3.3 Split-Supply Operation
      4. 8.3.4 Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RYP|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.9 Typical Characteristics: S2D Configuration

at TA = 25℃, VS+ = 5V, VS– = 0V, floating VOCM, PD, and MODE pins, VICM = mid-supply, S2D ac-coupled input/output configuration with CSH = Open, RTERM = 50Ω, ZS = 50Ω, ZL = 100Ω (see Figure 8-4), input and outputs de-embedded up to the device pins, and ambient temperatures shown (unless otherwise noted)

TRF1305A2 Power Gain (Sds21) Across Temperature
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-74 Power Gain (Sds21) Across Temperature
TRF1305A2 Input Return Loss (Sss11) Across Temperature
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-76 Input Return Loss (Sss11) Across Temperature
TRF1305A2 Output Return Loss (Sdd22) Across Temperature
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-78 Output Return Loss (Sdd22) Across Temperature
TRF1305A2 Reverse Isolation (Ssd12) Across Temperature
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-80 Reverse Isolation (Ssd12) Across Temperature
TRF1305A2 OIP3 Across Temperature
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-82 OIP3 Across Temperature
TRF1305A2 OIP3 Across Temperature
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-84 OIP3 Across Temperature
TRF1305A2 IMD3 Lower Across Temperature
At (2f1 – f2) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-86 IMD3 Lower Across Temperature
TRF1305A2 IMD3 Higher Across Temperature
At (2f2 – f1) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-88 IMD3 Higher Across Temperature
TRF1305A2 IMD3 Lower Across Temperature
At (2f1 – f2) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-90 IMD3 Lower Across Temperature
TRF1305A2 IMD3 Higher Across Temperature
At (2f2 – f1) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-92 IMD3 Higher Across Temperature
TRF1305A2 OIP2 Across Temperature
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-94 OIP2 Across Temperature
TRF1305A2 OIP2 Across Temperature
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-96 OIP2 Across Temperature
TRF1305A2 IMD2 Lower Across Temperature
At (f2 – f1) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-98 IMD2 Lower Across Temperature
TRF1305A2 IMD2 Higher Across Temperature
At (f1 + f2) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-100 IMD2 Higher Across Temperature
TRF1305A2 IMD2 Lower Across Temperature
At (f2 – f1) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-102 IMD2 Lower Across Temperature
TRF1305A2 IMD2 Higher Across Temperature
At (f1 + f2) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-104 IMD2 Higher Across Temperature
TRF1305A2 HD2 Across Temperature
PO = 7dBm
Figure 6-106 HD2 Across Temperature
TRF1305A2 HD2 Across Temperature
PO = 1dBm
Figure 6-108 HD2 Across Temperature
TRF1305A2 HD3 Across Temperature
PO = 7dBm
Figure 6-110 HD3 Across Temperature
TRF1305A2 HD3 Across Temperature
PO = 1dBm
Figure 6-112 HD3 Across Temperature
TRF1305A2 OP1dB Across Temperature
 
Figure 6-114 OP1dB Across Temperature
TRF1305A2 Noise Figure Across Temperature
 
Figure 6-116 Noise Figure Across Temperature
TRF1305A2 Step Response
DC-coupled, VS+ = 2.5V, VS– = –2.5V
Figure 6-118 Step Response
TRF1305A2 Power Up and Power Down Timing
DC-coupled, VS+ = 2.5V, VS– = –2.5V
Figure 6-120 Power Up and Power Down Timing
TRF1305A2 Differential Output Power Across Single-Ended Input Power, Ch1
 
Figure 6-122 Differential Output Power Across Single-Ended Input Power, Ch1
TRF1305A2 Common-Mode Rejection Ratio (CMRR)
PIN = –20dBm at each driven input pin with 50Ω source
Figure 6-124 Common-Mode Rejection Ratio (CMRR)
TRF1305A2 Amplitude Imbalance
PIN = –20dBm at each driven input pin with 50Ω source
Figure 6-126 Amplitude Imbalance
TRF1305A2 Overdrive Recovery Response, Ch1
DC-coupled, VS+ = 2.5V, VS– = –2.5V, 2 to 5 times output voltages are with an input voltage 2 to 5 times of VIN as shown, respectively
Figure 6-128 Overdrive Recovery Response, Ch1
TRF1305A2 Crosstalk
PIN = –20dBm at each driven input pin with 50Ω source
Figure 6-130 Crosstalk
TRF1305A2 Power Gain (Sds21) Across Supply Voltage
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-75 Power Gain (Sds21) Across Supply Voltage
TRF1305A2 Input Return Loss (Sss11) Across Supply Voltage
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-77 Input Return Loss (Sss11) Across Supply Voltage
TRF1305A2 Output Return Loss (Sdd22) Across Supply Voltage
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-79 Output Return Loss (Sdd22) Across Supply Voltage
TRF1305A2 Reverse Isolation (Ssd12) Across Supply Voltage
PIN = –20dBm with 50Ω source at all excited ports,
nonexcited ports are terminated with 50Ω
Figure 6-81 Reverse Isolation (Ssd12) Across Supply Voltage
TRF1305A2 OIP3 Across Supply Voltage
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-83 OIP3 Across Supply Voltage
TRF1305A2 OIP3 Across Supply Voltage
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-85 OIP3 Across Supply Voltage
TRF1305A2 IMD3 Lower Across Supply Voltage
At (2f1 – f2) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-87 IMD3 Lower Across Supply Voltage
TRF1305A2 IMD3 Higher Across Supply Voltage
At (2f2 – f1) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-89 IMD3 Higher Across Supply Voltage
TRF1305A2 IMD3 Lower Across Supply Voltage
At (2f1 – f2) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-91 IMD3 Lower Across Supply Voltage
TRF1305A2 IMD3 Higher Across Supply Voltage
At (2f2 – f1) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-93 IMD3 Higher Across Supply Voltage
TRF1305A2 OIP2 Across Supply Voltage
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-95 OIP2 Across Supply Voltage
TRF1305A2 OIP2 Across Supply Voltage
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-97 OIP2 Across Supply Voltage
TRF1305A2 IMD2 Lower Across Supply Voltage
At (f2 – f1) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-99 IMD2 Lower Across Supply Voltage
TRF1305A2 IMD2 Higher Across Supply Voltage
At (f1 + f2) frequency where f1 < f2,
PO = 1dBm/tone, 2MHz tone spacing
Figure 6-101 IMD2 Higher Across Supply Voltage
TRF1305A2 IMD2 Lower Across Supply Voltage
At (f2 – f1) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-103 IMD2 Lower Across Supply Voltage
TRF1305A2 IMD2 Higher Across Supply Voltage
At (f1 + f2) frequency where f1 < f2,
PO = –5dBm/tone, 2MHz tone spacing
Figure 6-105 IMD2 Higher Across Supply Voltage
TRF1305A2 HD2 Across Supply Voltage
PO = 7dBm
Figure 6-107 HD2 Across Supply Voltage
TRF1305A2 HD2 Across Supply Voltage
PO = 1dBm
Figure 6-109 HD2 Across Supply Voltage
TRF1305A2 HD3 Across Supply Voltage
PO = 7dBm
Figure 6-111 HD3 Across Supply Voltage
TRF1305A2 HD3 Across Supply Voltage
PO = 1dBm
Figure 6-113 HD3 Across Supply Voltage
TRF1305A2 OP1dB Across Supply Voltage
 
Figure 6-115 OP1dB Across Supply Voltage
TRF1305A2 Noise Figure Across Supply Voltage
 
Figure 6-117 Noise Figure Across Supply Voltage
TRF1305A2 Step Response
DC-coupled, VS+ = 2.5V, VS– = –2.5V
Figure 6-119 Step Response
TRF1305A2 Power Up and Power Down Timing
DC-coupled, VS+ = 2.5V, VS– = –2.5V
Figure 6-121 Power Up and Power Down Timing
TRF1305A2 Differential Output Power Across Single-Ended Input Power, Ch2
 
Figure 6-123 Differential Output Power Across Single-Ended Input Power, Ch2
TRF1305A2 Gain and Phase Mismatch Between Channels
PIN = –20dBm at each driven input pin with 50Ω source
Figure 6-125 Gain and Phase Mismatch Between Channels
TRF1305A2 Phase Imbalance
PIN = –20dBm at each driven input pin with 50Ω source
Figure 6-127 Phase Imbalance
TRF1305A2 Overdrive Recovery Response, Ch2
DC-coupled, VS+ = 2.5V, VS– = –2.5V, 2 to 5 times output voltages are with an input voltage 2 to 5 times of VIN as shown, respectively
Figure 6-129 Overdrive Recovery Response, Ch2