6.12.3 Parallel Interface Mode
In parallel mode, the start condition is generated on the rising edge of the I/O_7 pin while the CLK is high.
This is used to reset the interface logic. Figure 6-11, Figure 6-12, and Figure 6-13 show the sequence of the data, with an 8-bit address word first, followed by data.
Communication is ended by:
- The StopSmpl condition, where a falling edge on the I/O_7 pin is expected while CLK is high
- The StopCont condition, where the I/O_7 pin must have a successive rising and falling edge while CLK is low to reset the parallel interface and be ready for the new communication sequence
- The StopSmpl condition is also used to terminate the direct mode.
Figure 6-11 Parallel Interface Communication With Simple Stop Condition (StopSmpl)
Figure 6-12 Parallel Interface Communication With Continuous Stop Condition (StopCont)
Figure 6-13 Parallel Interface Communication With Continuous Stop Condition