SLOS758G December 2011 – March 2020 TRF7963A
When an SPI interface is used, I/O pins I/O_2, I/O_1, and I/O_0 must be hard-wired as specified in Table 6-6. On power up, the TRF7963A looks for the status of these pins; if they are not the same (not all high, or not all low), the reader enters into one of two possible SPI modes:
The choice of one of these modes over the other should be made based on the available GPIOs and the desired control of the system.
The serial communications work in the same manner as the parallel communications with respect to the FIFO, except for the following condition. On receiving an IRQ from the reader, the MCU reads the TRF7963A IRQ Status register to determine how to service the reader. After this, the MCU must to do a dummy read to clear the reader's IRQ Status register. The dummy read is required in SPI mode, because the reader's IRQ Status register needs an additional clock cycle to clear the register. This is not required in parallel mode, because the additional clock cycle is included in the Stop condition.
A procedure for a dummy read is as follows: