SLUS223G April   1997  – July 2022 UC1842 , UC1843 , UC1844 , UC1845 , UC2842 , UC2843 , UC2844 , UC2845 , UC3842 , UC3843 , UC3844 , UC3845


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. COMP
        2. VFB
        3. ISENSE
        4. RT/CT
        5. GROUND
        6. OUTPUT
        7. VCC
        8. VREF
      2. 8.3.2  Pulse-by-Pulse Current Limiting
      3. 8.3.3  Current-Sense
      4. 8.3.4  Error Amplifier With Low Output Resistance
      5. 8.3.5  Undervoltage Lockout
      6. 8.3.6  Oscillator
      7. 8.3.7  Synchronization
      8. 8.3.8  Shutdown Technique
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Soft Start
      11. 8.3.11 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Open-Loop Test Fixture
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1.  Input Bulk Capacitor and Minimum Bulk Voltage
        2.  Transformer Turns Ratio and Maximum Duty Cycle
        3.  Transformer Inductance and Peak Currents
        4.  Output Capacitor
        5.  Current Sensing Network
        6.  Gate Drive Resistor
        7.  VREF Capacitor
        8.  RT/CT
        9.  Start-Up Circuit
        10. Voltage Feedback Compensation
          1. Power Stage Poles and Zeroes
          2. Slope Compensation
          3. Open-Loop Gain
          4. Compensation Loop
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Feedback Traces
      2. 11.1.2 Bypass Capacitors
      3. 11.1.3 Compensation Components
      4. 11.1.4 Traces and Ground Planes
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


The oscillator allows for up to 500-kHz switching frequency. The OUTPUT gate drive is the same frequency as the oscillator in the UCx842 and UCx843 devices and can operate near 100% duty cycle. In the UCx844 and UCx845 devices, the frequency of OUTPUT is one-half that of the oscillator due to an internal T flipflop that blanks the output off every other clock cycle, resulting in a maximum duty cycle for these devices of < 50% of the switching frequency. An external resistor, RRT, connected from VREF to RT/CT sets the charging current for the timing capacitor, CCT, which is connected from RT/CT to GROUND. An RRT value greater than 5 kΩ is recommended on RT/CT to set the positive ramp time of the internal oscillator. Using a value of 5 kΩ or greater for RRT maintains a favorable ratio between the internal impedance and the external oscillator set resistor and results in minimal change in frequency over temperature. Using a value of less the recommended minimum value may result in frequency drift over temperature, part tolerances, or process variations.

The peak-to-peak amplitude of the oscillator waveform is 1.7 V in UCx84x devices. The UCx842 and UCx843 have a maximum duty cycle of approximately 100%, whereas the UCx844 and UCx845 are clamped to 50% maximum by an internal toggle flip flop. This duty cycle clamp is advantageous in most flyback and forward converters. For optimum IC performance the dead-time should not exceed 15% of the oscillator clock period. The discharge current, typically 6 mA at room temperature, sets the dead time, see Figure 7-9. During the discharge, or dead time, the internal clock signal blanks the output to the low state. This limits the maximum duty cycle DMAX to:

Equation 7. GUID-F8DD916A-BB28-419F-A485-A2E39D1A1705-low.gif

Equation 8 applies to UCx842 and UCx843 units because the OUTPUT switches at the same frequency as the oscillator and the maximum duty cycle can be as high as 100%.

Equation 8. GUID-503D860B-032B-4674-8968-5C0B9AD5DE67-low.gif

Equation 8 applies to UCx844 and UCx845 units because the OUTPUT switches at half the frequency as the oscillator and the maximum duty cycle can be as high as 50%.

When the power transistor turns off, a noise spike is coupled to the oscillator RT/CT terminal. At high duty cycles, the voltage at RT/CT is approaching its threshold level (approximately 2.7 V, established by the internal oscillator circuit) when this spike occurs. A spike of sufficient amplitude prematurely trips the oscillator. To minimize the noise spike, choose CCT as large as possible, remembering that dead time increases with CCT. It is recommended that CCT never be less than approximately 1000 pF. Often the noise which causes this problem is caused by the OUTPUT being pulled below ground at turnoff by external parasitics. This is particularly true when driving MOSFETs. A Schottky diode clamp from GROUND to OUTPUT prevents such output noise from feeding to the oscillator.

For RRT > 5 kΩ: GUID-A54D7569-34D9-48B6-8ED7-968CE8506C63-low.gif
Figure 8-8 Oscillator Section Schematic