The simplest method to force synchronization uses the timing capacitor, CCT, in near standard configuration. Rather than bring CCT to ground directly, a small resistor is placed in series with CCT to ground. This resistor serves as the input for the sync pulse which raises the CCT voltage above the oscillator’s internal upper threshold. The PWM is allowed to run at the frequency set by RRT and CCT until the sync pulse appears. This scheme offers several advantages including having the local ramp available for slope compensation. The UC3842/3/4/5 oscillator must be set to a lower frequency than the sync pulse stream, typically 20% with a 0.5-V pulse applied across the resistor.