SLUS223G April   1997  – July 2022

PRODUCTION DATA

1. Features
2. Applications
3. Description
4. Revision History
5. Device Comparison Table
6. Pin Configuration and Functions
7. Specifications
8. Detailed Description
1. 8.1 Overview
2. 8.2 Functional Block Diagrams
3. 8.3 Feature Description
4. 8.4 Device Functional Modes
9. Application and Implementation
1. 9.1 Application Information
2. 9.2 Typical Application
1. 9.2.1 Design Requirements
2. 9.2.2 Detailed Design Procedure
3. 9.2.3 Application Curves
10. 10Power Supply Recommendations
11. 11Layout
1. 11.1 Layout Guidelines
2. 11.2 Layout Example
12. 12Device and Documentation Support
13. 13Mechanical, Packaging, and Orderable Information

#### Package Options

• D|8
• D|14
• P|8
• D|8
• D|14
##### 9.2.2.10.2 Slope Compensation

Slope compensation is the large signal sub-harmonic instability that can occur with duty cycles that may extend beyond 50% where the rising primary side inductor current slope may not match the falling secondary side current slope. The sub-harmonic oscillation would result in an increase in the output voltage ripple and may even limit the power handling capability of the converter.

The target of slope compensation is to achieve an ideal quality coefficient, QP , to be equal to 1 at half of the switching frequency. The QP is calculated with Equation 37.

Equation 37. In Equation 37, D is the primary side switch duty cycle and MC is the slope compensation factor, which is defined with Equation 38.

Equation 38. In Equation 38, Se is the compensation ramp slope and the Sn is the inductor rising slope. The optimal goal of the slope compensation is to achieve QP equal to 1; upon rearranging Equation 38 the ideal value of slope compensation factor is determined:

Equation 39. For this design to have adequate slope compensation, MC must be 2.193 when D reaches it maximum value of 0.627.

The inductor rising slope, Sn, at the ISENSE pin is calculated with Equation 40.

Equation 40. The compensation slope, Se, is calculated with Equation 41.

Equation 41. The compensation slope is added into the system through RRAMP and RCSF. The CRAMP is an AC-coupling capacitor that allows the voltage ramp of the oscillator to be used without adding an offset to the current sense; select a value to approximate high frequency short circuit, such as 10 nF as a starting point and make adjustments if required. The RRAMP and RCSF resistors form a voltage divider from the oscillator charge slope and this proportional ramp is injected into the ISENSE pin to add slope compensation. Choose the value of RRAMP to be much larger than the RRT resistor so that it does not load down the internal oscillator and result in a frequency shift.  The oscillator charge slope is calculated using the peak-to-peak voltage of the RT/CT sawtooth waveform, VOSCpp, equal to 1.7 V, and the minimum on-time, as shown in Equation 43.

Equation 42. Equation 43. To achieve a 44.74-mV/µs compensation slope, RCSF resistor is calculated with Equation 44. In this design, RRAMP is selected as 24.9 kΩ, a 4.2-kΩ resistor was selected for RCSF.

Equation 44. 