SLUSA12F December   2009  – October 2020 UCC28C40-Q1 , UCC28C41-Q1 , UCC28C42-Q1 , UCC28C43-Q1 , UCC28C44-Q1 , UCC28C45-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. COMP
        2. FB
        3. CS
        4. RT/CT
        5. GND
        6. OUT
        7. VDD
        8. VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1.  Custom Design With WEBENCH® Tools
        2.  Input Bulk Capacitor and Minimum Bulk Voltage
        3.  Transformer Turns Ratio and Maximum Duty Cycle
        4.  Transformer Inductance and Peak Currents
        5.  Output Capacitor
        6.  Current Sensing Network
        7.  Gate Drive Resistor
        8.  VREF Capacitor
        9.  RT/CT
        10. Start-Up Circuit
        11. Voltage Feedback Compensation
          1. Power Stage Poles and Zeroes
          2. Slope Compensation
          3. Open-Loop Gain
          4. Compensation Loop
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Precautions
      2. 11.1.2 Feedback Traces
      3. 11.1.3 Bypass Capacitors
      4. 11.1.4 Compensation Components
      5. 11.1.5 Traces and Ground Planes
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Power Stage Poles and Zeroes

The first step in compensating a fixed frequency flyback is to verify if the converter is continuous conduction mode (CCM) or discontinuous conduction mode (DCM). If the primary inductance (LP) is greater than the inductance for DCM or CCM boundary mode operation, called the critical inductance (LPcrit), then the converter operates in CCM:

Equation 17. GUID-EEB9B69D-C2D2-4126-AD75-95C14EF391E3-low.gif
Equation 18. GUID-5A9C74EA-3B0A-46D8-8DA7-E869A836D081-low.gif

For the entire input voltage range, the selected inductor has a value larger than the critical inductor. Therefore, the converter operates in CCM and the compensation loop requires design based on CCM flyback equations.

The current-to-voltage conversion is done externally with the ground-referenced RCS and the internal 2R/R resistor divider which sets up the internal current sense gain, ACS = 3. The exact value of these internal resistors is not critical but thedeviceprovides tight control of the resistor divider ratio, so regardless of the actual resistor value variations their relative value to each other is maintained.

The DC open-loop gain (GO) of the fixed-frequency voltage control loop of a peak current mode control CCM flyback converter shown in Equation 19 is approximated by first using the output load (ROUT), the primary to secondary turns ratio (NPS), and the maximum duty cycle (D) as calculated in Equation 20.

Equation 19. GUID-7D978144-A0E9-4B82-91C0-639104B50C19-low.gif

In Equation 19, D is calculated with Equation 20, τL is calculated with Equation 21, and M is calculated with Equation 22.

Equation 20. GUID-C28BC9A7-2A6B-428F-9731-DC611D1C3CEC-low.gif
Equation 21. GUID-DF345C2C-3980-4358-A209-1AF55A0C7EE8-low.gif
Equation 22. GUID-0BD1F6B1-7305-40EE-B8CA-D86E38C9C39F-low.gif

For this design, a converter with an output voltage (VOUT) of 12 V, and 48 W relates to an output load (ROUT) equal to 3 Ω at full load. With a maximum duty cycle of 0.627, a current sense resistance of 0.75 Ω, and a primary to secondary turns-ratio of 10, the open-loop gain calculates to 3.082 or 9.776 dB.

A CCM flyback has two zeroes that are of interest. The ESR and the output capacitance contribute a left-half plane zero (ωESRz) to the power stage, and the frequency of this zero (fESRz), are calculated with Equation 23 and Equation 24.

Equation 23. GUID-E6FC3435-B8CD-4497-9C9E-127B8B464042-low.gif
Equation 24. GUID-2E4E838D-3DF0-442B-A2F6-2430EF3F691D-low.gif

The fESRz zero for an output capacitance of 2200 µF and a total ESR of 43 mΩ is located at 1.682 kHz.

CCM flyback converters have a zero in the right-half plane (RHP) in their transfer function. A RHP zero has the same 20 dB per decade rising gain magnitude with increasing frequency just like a left-half plane zero, but it adds a 90° phase lag instead of lead. This phase lag tends to limit the overall loop bandwidth. The frequency location (fRHPz) of the RHP zero (ωRHPz) is a function of the output load, the duty cycle, the primary inductance (LP), and the primary to secondary side turns ratio (NPS).

Equation 25. GUID-E010E5C7-D14E-47AC-802E-AA7FC885B984-low.gif
Equation 26. GUID-9670C978-D045-401A-A407-6C49209347E5-low.gif

The right-half plane zero frequency increases with higher input voltage and lighter load. Generally, the design requires consideration of the worst case of the lowest right-half plane zero frequency and the converter must be compensated at the minimum input and maximum load condition. With a primary inductance of 1.5 mH, at 75-V DC input, the RHP zero frequency (fRHPz) is equal to 7.07 kHz at maximum duty cycle, full load.

The power stage has one dominate pole (ωP1) which is in the region of interest, located at a lower frequency (fP1); which is related to the duty cycle, the output load, and the output capacitance, and calculated with Equation 28. There is also a double pole placed at half the switching frequency of the converter (fP2) calculated with Equation 30. For this example, pole fP1 is located at 40.37 Hz and fP2 is at 55 kHz.

Equation 27. GUID-86EA56C5-6ED8-48FF-BD32-80F6298E1F03-low.gif
Equation 28. GUID-4FC74391-7A0A-4415-BF3B-10DC7F3CD77A-low.gif
Equation 29. GUID-E0A9426B-9C7F-43B3-B57E-EB57D8D18FF4-low.gif
Equation 30. GUID-3D0F36C9-C607-435A-8611-8E5A553B9F9C-low.gif