SLUSA12F December   2009  – October 2020 UCC28C40-Q1 , UCC28C41-Q1 , UCC28C42-Q1 , UCC28C43-Q1 , UCC28C44-Q1 , UCC28C45-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Input Bulk Capacitor and Minimum Bulk Voltage
        3. 9.2.2.3  Transformer Turns Ratio and Maximum Duty Cycle
        4. 9.2.2.4  Transformer Inductance and Peak Currents
        5. 9.2.2.5  Output Capacitor
        6. 9.2.2.6  Current Sensing Network
        7. 9.2.2.7  Gate Drive Resistor
        8. 9.2.2.8  VREF Capacitor
        9. 9.2.2.9  RT/CT
        10. 9.2.2.10 Start-Up Circuit
        11. 9.2.2.11 Voltage Feedback Compensation
          1. 9.2.2.11.1 Power Stage Poles and Zeroes
          2. 9.2.2.11.2 Slope Compensation
          3. 9.2.2.11.3 Open-Loop Gain
          4. 9.2.2.11.4 Compensation Loop
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Precautions
      2. 11.1.2 Feedback Traces
      3. 11.1.3 Bypass Capacitors
      4. 11.1.4 Compensation Components
      5. 11.1.5 Traces and Ground Planes
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Compensation Loop

The design of the compensation loop involves selecting the appropriate components so that the required gain, poles, and zeros can be designed to result in a stable system over the entire operating range. There are three distinct portions of the loop: the TL431A-Q1 (or TL431B-Q1), the opto-coupler, and the error amplifier. Each of these stages combines with the power stage to result in a stable robust system.

For good transient response, the bandwidth of the finalized design must be as large as possible. The bandwidth of a CCM flyback, fBW, is limited to ¼ of the RHP zero frequency, or approximately 1.77 kHz using Equation 41.

Equation 41. GUID-257D47FD-36F9-4621-9004-B777EC7FFAB4-low.gif

The gain of the open-loop power stage at fBW can be calculated using Equation 40 or can be observed on the Bode plot (Figure 9-3) and is equal to –19.55 dB and the phase at fBW is equal to –58°.

The secondary side portion of the compensation loop begins with establishing the regulated steady state output voltage. To set the regulated output voltage, a TL431A-Q1 (or TL431B-Q1) adjustable precision shunt regulator is ideally suited for use on the secondary side of isolated converters due to its accurate voltage reference and internal op-amp. The resistors used in the divider from the output terminals of the converter to the TL431A-Q1 (or TL431B-Q1) REF pin are selected based upon the desired power consumption. Because the REF input current for the TL431A-Q1 (or TL431B-Q1) is only 2 µA, selecting the resistors for a divider current (IFB_REF) of 1 mA results in minimal error. The top divider resistor (RFBU) is calculated:

Equation 42. GUID-47856D99-A1DC-4406-90B1-85115E2162CF-low.gif

The TL431A-Q1 (or TL431B-Q1) reference voltage (REFTL431) has a typical value of 2.495 V. A 9.53-kΩ resistor is chosen for RFBU. To set the output voltage to 12 V, 2.49 kΩ is used for RFBB.

Equation 43. GUID-79F1E77B-E155-418F-AB49-6F3D1A4FDD62-low.gif

For good phase margin, a compensator zero (fCOMPz) is required and should be placed at 1/10th the desired bandwidth:

Equation 44. GUID-8776F4EA-461A-41A1-AB84-F93F4135DF67-low.gif
Equation 45. GUID-9CF9A024-CB3E-428A-9233-517CFB3F4287-low.gif

With this converter, fCOMPz should be set at approximately 177 Hz. A series resistor (RCOMPz) and capacitor (CCOMPz) placed across the TL431A-Q1 (or TL431B-Q1) cathode to REF sets the compensator zero location. Setting CCOMPz to 0.01 µF, RCOMPz is calculated:

Equation 46. GUID-6ED5DF8E-C630-45E9-AC87-20A746D99CEB-low.gif

Using a standard value of 88.7 kΩ for RZ and a 0.01 µF for CZ results in a zero placed at 179 Hz.

In Figure 9-2, RTLbias provides cathode current to the TL431A-Q1 (or TL431B-Q1) from the regulated voltage provided from the Zener diode (DREG). For robust performance, 10 mA is provided to bias the TL431A-Q1 (TL431B-Q1) by way of the 10-V Zener and a 1-kΩ resistor is used for RTLbias.

The gain of the TL431A-Q1 (or TL431B-Q1) portion of the compensation loop is calculated with Equation 47.

Equation 47. GUID-2374D474-8C05-454D-ACE6-F99265F7905A-low.gif

A compensation pole is required at the frequency of right half plane zero or the ESR zero, whichever is lowest. Based previous the analysis, the right half plane zero (fRHPz) is located at 7.07 kHz and the ESR zero (fESRz) is at 1.68 kHz; therefore, for this design, the compensation pole must be put at 1.68 kHz. The opto-coupler contains a parasitic pole that is difficult to characterize over frequency so the opto-coupler is set up with a pull-down resistor (ROPTO) equal to 1 kΩ, which moves the parasitic opto-coupler pole further out and beyond the range of interest for this design.

The required compensation pole can be added to the primary side error amplifier using RCOMPp and CCOMPp. Choosing RCOMPp as 10 kΩ, the required value of CCOMPp is determined using Equation 48.

Equation 48. GUID-A9FE4B78-6D29-47CC-A923-861BE77E7981-low.gif

A 10-nF capacitor is used for CCOMPp setting the compensation pole at 1.59 kHz.

Adding a DC gain to the primary-side error amplifier may be required to obtain the required bandwidth and helps to adjust the loop gain as needed. Using 4.99 kΩ for RFBG sets the DC gain on the error amplifier to 2. At this point the gain transfer function of the error amplifier stage (GEA(s)) of the compensation loop can be characterized using Equation 49.

Equation 49. GUID-6A0351D4-F66D-493A-A705-D79851D0CC50-low.gif

Using an opto-coupler whose current transfer ratio (CTR) is typically at 100% in the frequency range of interest so that CTR = 1, the transfer function of the opto-coupler stage (GOPTO(s)) is found using Equation 50.

Equation 50. GUID-48C43BB8-55C4-4CC2-AC27-64EF5599373D-low.gif

The bias resistor (RLED) to the internal diode of the opto-coupler and the pull-down resistor on the opto emitter (ROPTO) sets the gain across the isolation boundary. ROPTO has already been set to 1 kΩ but the value of RLED has not yet been determined.

The total closed loop gain (GTOTAL(s)) is the combination of the open-loop power stage (Ho(s)), the opto gain (GOPTO(s)), the error amplifier gain (GEA(s)), and the gain of the TL431A-Q1 (or TL431B-Q1) stage (GTL431(s)), as shown in Equation 51.

Equation 51. GUID-E837ABF4-225A-44DF-8DA8-2F5F6629BA3B-low.gif

The required value for RLED can be selected to achieve the desired crossover frequency (fBW). By setting the total loop gain equal to 1 at the desired crossover frequency and rearranging Equation 51, the optimal value for RLED can be determined, as shown in Equation 52.

Equation 52. GUID-4CF99D16-0B3F-421F-8DAE-7C1E1AFA1A27-low.gif

A 1.3-kΩ resistor suits the requirement for RLED.

Based on the compensation loop structure, the entire compensation loop transfer function is written as Equation 53.

Equation 53. GUID-4204B502-9D99-4E66-A107-47D44154DDF9-low.gif

The final closed-loop bode plots are show in Figure 9-5 and Figure 9-6. The converter achieves a crossover frequency of approximately 1.8 kHz and has a phase margin of approximately 67°.

TI recommends checking the loop stability across all the corner cases including component tolerances to ensure system stability.

GUID-859659A5-98A2-4FA3-B052-D894BFF1B7D3-low.gifFigure 9-5 Converter Closed-Loop Bode Plot – Gain
GUID-5805238B-3FF1-4CA7-A004-763056E5836D-low.gifFigure 9-6 Converter Closed-Loop Bode Plot – Phase