SLUSA12F December   2009  – October 2020 UCC28C40-Q1 , UCC28C41-Q1 , UCC28C42-Q1 , UCC28C43-Q1 , UCC28C44-Q1 , UCC28C45-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Input Bulk Capacitor and Minimum Bulk Voltage
        3. 9.2.2.3  Transformer Turns Ratio and Maximum Duty Cycle
        4. 9.2.2.4  Transformer Inductance and Peak Currents
        5. 9.2.2.5  Output Capacitor
        6. 9.2.2.6  Current Sensing Network
        7. 9.2.2.7  Gate Drive Resistor
        8. 9.2.2.8  VREF Capacitor
        9. 9.2.2.9  RT/CT
        10. 9.2.2.10 Start-Up Circuit
        11. 9.2.2.11 Voltage Feedback Compensation
          1. 9.2.2.11.1 Power Stage Poles and Zeroes
          2. 9.2.2.11.2 Slope Compensation
          3. 9.2.2.11.3 Open-Loop Gain
          4. 9.2.2.11.4 Compensation Loop
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Precautions
      2. 11.1.2 Feedback Traces
      3. 11.1.3 Bypass Capacitors
      4. 11.1.4 Compensation Components
      5. 11.1.5 Traces and Ground Planes
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

VVDD = 15 V(1), RRT = 10 kΩ, CCT = 3.3 nF, CVDD = 0.1 µF and no load on the outputs, TA = –40°C to 125°C (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
REFERENCE
VVREFVREF voltage, initial accuracyIOUT = 1 mA4.955.1V
Line regulationVVDD = 12 V to 18 V0.220mV
Load regulation1 mA to 20 mA325mV
Temperature stabilitySee (2)0.20.4mV/°C
Total output variationSee (2)4.825.18V
VREF noise voltage10 Hz to 10 kHz, TA = 25°C, see (2)50µV
Long term stability1000 hours, TA = 125°C, see (2)525mV
IVREFOutput short circuit–30–45–55mA
OSCILLATOR
fOSCInitial accuracyTA = 25°C, see (3)50.55355kHz
TA = Full Range, see (3)50.557kHz
Voltage stability12 V ≤ VVDD ≤ 18 V0.2%1%
Temperature stabilityTA(MIN) to TA(MAX), see (2)1%2.5%
AmplitudeRT/CT pin peak-to-peak voltage1.9V
Discharge currentTA = 25°C, VRT/CT = 2 V, see (4)7.78.49mA
TA = Full Range, VRT/CT = 2 V, see (4)7.28.49.5
ERROR AMPLIFIER
VFBFeedback input voltage, initial accuracyTA = 25°C, VCOMP = 2.5 V2.4752.52.525V
Feedback input voltage, total variationTA = Full Range, VCOMP = 2.5 V2.452.52.55V
IFBInput bias currentVFB = 5 V–0.1–2µA
AVOLOpen-loop voltage gain2 V ≤ VOUT ≤ 4 V6590dB
Unity gain bandwidthSee (2)11.5MHz
PSRRPower supply rejection ratio12 V ≤ VVDD ≤ 18 V60dB
Output sink currentVFB = 2.7 V, VCOMP = 1.1 V214mA
Output source currentVFB = 2.3 V, VCOMP = 5 V–0.5–1mA
VOHHigh-level COMP voltageVFB = 2.7 V, RCOMP = 15 kΩ COMP to GND56.8V
VOLLow-level COMP voltageVFB = 2.7 V, RCOMP = 15 kΩ COMP to VREF0.11.1V
CURRENT SENSE
ACSGainTA = 25°C, See (5)(6)2.8533.15V/V
TA = Full Range, See (5)(6)2.7533.15V/V
VCSMaximum input signalVFB < 2.4 V0.911.1V
PSRRPower supply rejection ratioVVDD = 12 V to 18 V(2)(5)70dB
ICSInput bias current–0.1–2µA
tDCS to output delay3570ns
COMP to CS offsetVCS = 0 V1.15V
OUTPUT
VOUT(low)RDS(on) pulldownISINK = 200 mA5.515Ω
VOUT(high)RDS(on) pullupISOURCE = 200 mA1025Ω
tRISERise tImeCOUT = 1 nF2550ns
tFALLFall tImeCOUT = 1 nF2040ns
UNDERVOLTAGE LOCKOUT
VDDONStart thresholdUCC28C42-Q1, UCC28C44-Q113.514.515.5V
UCC28C43-Q1, UCC28C45-Q17.88.49
UCC28C40-Q1, UCC28C41-Q16.577.5
VDDOFFMinimum operating voltageUCC28C42-Q1, UCC28C44-Q18910V
UCC28C43-Q1, UCC28C45-Q177.68.2
UCC28C40-Q1, UCC28C41-Q16.16.67.1
PWM
DMAXMaximum duty cycleUCC28C42-Q1, UCC28C43-Q1, UCC28C40-Q1, VFB < 2.4 V94%96%
UCC28C44-Q1, UCC28C45-Q1, UCC28C41-Q1, VFB < 2.4 V47%48%
DMINMinimum duty cycleVFB > 2.6 V0%
CURRENT SUPPLY
ISTART-UPStart-up currentVVDD = VDDON – 0.5 V50100µA
IVDDOperating supply currentVFB = VCS = 0 V2.33mA
Adjust VVDD above the start threshold before setting at 15.5 V.
Ensured by design. Not production tested.
Output frequencies of the UCC28C41-Q1, UCC28C44-Q1, and the UCC28C45-Q1 are half the oscillator frequency.
Oscillator discharge current is measured with RRT = 10 kΩ to VREF.
Parameter measured at trip point of latch with VFB = 0 V.
Gain is defined as ACS = ΔVCOMP / ΔVCS , 0 V ≤ VCS ≤ 900 mV