SLUSA12F December   2009  – October 2020 UCC28C40-Q1 , UCC28C41-Q1 , UCC28C42-Q1 , UCC28C43-Q1 , UCC28C44-Q1 , UCC28C45-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Detailed Pin Description
        1. 8.3.1.1 COMP
        2. 8.3.1.2 FB
        3. 8.3.1.3 CS
        4. 8.3.1.4 RT/CT
        5. 8.3.1.5 GND
        6. 8.3.1.6 OUT
        7. 8.3.1.7 VDD
        8. 8.3.1.8 VREF
      2. 8.3.2  Undervoltage Lockout
      3. 8.3.3  ±1% Internal Reference Voltage
      4. 8.3.4  Current Sense and Overcurrent Limit
      5. 8.3.5  Reduced-Discharge Current Variation
      6. 8.3.6  Oscillator Synchronization
      7. 8.3.7  Soft Start
      8. 8.3.8  Enable and Disable
      9. 8.3.9  Slope Compensation
      10. 8.3.10 Voltage Mode
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 UVLO Mode
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Input Bulk Capacitor and Minimum Bulk Voltage
        3. 9.2.2.3  Transformer Turns Ratio and Maximum Duty Cycle
        4. 9.2.2.4  Transformer Inductance and Peak Currents
        5. 9.2.2.5  Output Capacitor
        6. 9.2.2.6  Current Sensing Network
        7. 9.2.2.7  Gate Drive Resistor
        8. 9.2.2.8  VREF Capacitor
        9. 9.2.2.9  RT/CT
        10. 9.2.2.10 Start-Up Circuit
        11. 9.2.2.11 Voltage Feedback Compensation
          1. 9.2.2.11.1 Power Stage Poles and Zeroes
          2. 9.2.2.11.2 Slope Compensation
          3. 9.2.2.11.3 Open-Loop Gain
          4. 9.2.2.11.4 Compensation Loop
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Precautions
      2. 11.1.2 Feedback Traces
      3. 11.1.3 Bypass Capacitors
      4. 11.1.4 Compensation Components
      5. 11.1.5 Traces and Ground Planes
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Reduced-Discharge Current Variation

The UCC28C4x-Q1 oscillator design incorporates a trimmed discharge current to accurately program maximum duty cycle and operating frequency. In its basic operation, a timing capacitor (CCT) is charged by a current source, formed by the timing resistor (RRT) connected to the device’s reference voltage (VREF). The oscillator design incorporates comparators to monitor the amplitude of the timing capacitor’s voltage. The exponentially shaped waveform charges up to a specific amplitude representing the oscillator’s upper threshold of 2.5 V. Once reached, an internal current sink to ground is turned on and the capacitor begins discharging. This discharge continues until the oscillator’s lower threshold has reached 0.7 V at which point the current sink is turned off. Next, the timing capacitor starts charging again and a new switching cycle begins.

GUID-77F51F79-CBFB-4520-B6DC-9D4DEE409897-low.gifFigure 8-4 Oscillator Circuit

While the device is discharging the timing capacitor, resistor RRT is also still trying to charge CCT. It is the exact ratio of these two currents, the discharging versus the charging current, which specifies the maximum duty cycle. During the discharge time of CCT, the device’s output is always off. This represents an ensured minimum off time of the switch, commonly referred to as dead-time. To program an accurate maximum duty cycle, use the information provided in Figure 7-15 for maximum duty cycle versus oscillator frequency. Any number of maximum duty cycles can be programmed for a given frequency by adjusting the values of RRT and CCT. Once RRT is selected, the oscillator timing capacitor can be found using the curves in Figure 7-1. However, because resistors are available in more precise increments, typically 1%, and capacitors are only available in 5% accuracy, it might be more practical to select the closest capacitor value first and then calculate the timing resistor value next.