8.6.42 JCTRL Register (Address = 0x204) [reset = 0x02]
JCTRL is shown in Figure 65 and described in Table 101.
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JESD204C Control (default: 0x02)
Figure 65. JCTRL Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
ALT_LANES |
SYNC_SEL |
SFORMAT |
SCR |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x1 |
R/W-0x0 |
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Table 101. JCTRL Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7:5 |
RESERVED |
R/W |
0x0 |
|
4 |
ALT_LANES |
R/W |
0x0 |
0 : Normal lane mapping (default). Link A uses lanes DA0 to DA3 and link B uses lanes DB0 to DB3. Other lanes are powered down.
1 : Alternate lane mapping (use upper lanes). Link A uses lanes DA4 to DA7 and link B uses lanes DB4 to DB7. Lanes DA0 to DA3 and DB0 to DB3 are powered down.
Note: This option is only supported when JMODE selects a mode that uses 8 or less lanes. The behavior is undefined for modes that do not meet this requirement.
|
3:2 |
SYNC_SEL |
R/W |
0x0 |
0 : Use the SYNCSE input for SYNC~ function (default)
1 : Use the TMSTP input for SYNC~ function. TMSTP_RECV_EN must also be set.
2 : Do not use any sync input pin (use software SYNC~ through JSYNC_N)
|
1 |
SFORMAT |
R/W |
0x1 |
Output sample format for JESD204C samples
0 : Offset binary
1 : Signed 2’s complement (default)
|
0 |
SCR |
R/W |
0x0 |
0 : 8B/10B Scrambler disabled (default) (applies only to 8B/10B modes)
1 : 8b/10b Scrambler enabled
Note 1: 64B/66B modes always use scrambling. This register does not apply to 64B/66B modes.
Note 2: This register should only be changed when JESD_EN is 0.
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