JAJSEY1C April 2019 – March 2022 ADC12DJ5200RF
Test modes are enabled by setting JTEST (see the JESD204C test pattern control register) to the desired test mode. Each test mode is described in detail in the following sections. Regardless of the test mode, the serializer outputs (number of lanes, rate) are powered up based on JMODE. Only enable the test modes when the JESD204C link is disabled. Figure 7-24 provides a diagram showing the various test mode insertion points.