| 15:8 |
TAD_COARSE |
R/W |
0x0 |
This register controls the sampling aperture delay adjustment when SRC_EN=0. Use this register to manually control the DEVCLK aperture delay when SYSREF Calibration is disabled. If ADC calibration or JESD204B is running, it is recommended that you gradually increase or decrease this value (1 code at a time) to avoid clock glitches. Refer to Switching Characteristics for TAD_COARSE resolution.
If ADC calibration is enabled (CAL_EN=1), or the JESD204C link is enabled (JESD_EN=1), the following rules must be obeyed to avoid clock glitches and unpredictable behavior:
1. Do not change TAD_INV. You must program CAL_EN=0 and JESD_EN=0 before changing TAD_INV.
2. TAD_COARSE must be increased or decreased gradually (no more than 4 codes at a time). This rule can be obeyed manually via SPI writes, or by setting TAD_RAMP_EN.
3. TAD_FINE may be changed to any value at any time (its adjustment is too fine to cause clock glitches).
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