JAJSEY1 April 2019 ADC12DJ5200RF
ADVANCE INFORMATION for pre-production products; subject to change without notice.
The clocking subsystem is largely responsible for achieving multi-device synchronization and deterministic latency. The ADC12DJ5200RF uses the JESD204C subclass-1 method to achieve deterministic latency and synchronization. Subclass 1 requires that the SYSREF signal be captured by a deterministic device clock (CLK±) edge at each system power-on and at each device in the system. This requirement imposes setup and hold constraints on SYSREF relative to CLK±, which can be difficult to meet at giga-sample clock rates over all system operating conditions. The ADC12DJ5200RF includes a number of features to simplify this synchronization process and to relax system timing constraints: