JAJSSH6 December   2023 MCT8315Z

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 SPI Secondary Device Mode Timings
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Stage
      2. 8.3.2  PWM Control Mode (1x PWM Mode)
        1. 8.3.2.1 Analog Hall Input Configuration
        2. 8.3.2.2 Digital Hall Input Configuration
        3. 8.3.2.3 Asynchronous Modulation
        4. 8.3.2.4 Synchronous Modulation
        5. 8.3.2.5 Motor Operation
      3. 8.3.3  Device Interface Modes
        1. 8.3.3.1 Serial Peripheral Interface (SPI)
        2. 8.3.3.2 Hardware Interface
      4. 8.3.4  Step-Down Mixed-Mode Buck Regulator
        1. 8.3.4.1 Buck in Inductor Mode
        2. 8.3.4.2 Buck in Resistor mode
        3. 8.3.4.3 Buck Regulator with External LDO
        4. 8.3.4.4 AVDD Power Sequencing on Buck Regulator
        5. 8.3.4.5 Mixed mode Buck Operation and Control
      5. 8.3.5  AVDD Linear Voltage Regulator
      6. 8.3.6  Charge Pump
      7. 8.3.7  Slew Rate Control
      8. 8.3.8  Cross Conduction (Dead Time)
      9. 8.3.9  Propagation Delay
        1. 8.3.9.1 Driver Delay Compensation
      10. 8.3.10 Pin Diagrams
        1. 8.3.10.1 Logic Level Input Pin (Internal Pulldown)
        2. 8.3.10.2 Logic Level Input Pin (Internal Pullup)
        3. 8.3.10.3 Open Drain Pin
        4. 8.3.10.4 Push Pull Pin
        5. 8.3.10.5 Four Level Input Pin
        6. 8.3.10.6 Seven Level Input Pin
      11. 8.3.11 Active Demagnetization
        1. 8.3.11.1 Automatic Synchronous Rectification Mode (ASR Mode)
          1. 8.3.11.1.1 Automatic Synchronous Rectification in Commutation
          2. 8.3.11.1.2 Automatic Synchronous Rectification in PWM Mode
        2. 8.3.11.2 Automatic Asynchronous Rectification Mode (AAR Mode)
      12. 8.3.12 Cycle-by-Cycle Current Limit
        1. 8.3.12.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
      13. 8.3.13 Hall Comparators (Analog Hall Inputs)
      14. 8.3.14 Advance Angle
      15. 8.3.15 FGOUT Signal
      16. 8.3.16 Protections
        1. 8.3.16.1  VM Supply Undervoltage Lockout (NPOR)
        2. 8.3.16.2  AVDD Undervoltage Lockout (AVDD_UV)
        3. 8.3.16.3  Buck Undervoltage Lockout (BUCK_UV)
        4. 8.3.16.4  VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 8.3.16.5  Overvoltage Protection (OVP)
        6. 8.3.16.6  Overcurrent Protection (OCP)
          1. 8.3.16.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.16.6.2 OCP Automatic Retry (OCP_MODE = 01b)
        7. 8.3.16.7  Buck Overcurrent Protection
        8. 8.3.16.8  Motor Lock (MTR_LOCK)
          1. 8.3.16.8.1 MTR_LOCK Latched Shutdown (MTR_LOCK_MODE = 00b)
          2. 8.3.16.8.2 MTR_LOCK Automatic Retry (MTR_LOCK_MODE = 01b)
          3. 8.3.16.8.3 MTR_LOCK Report Only (MTR_LOCK_MODE= 10b)
          4. 8.3.16.8.4 MTR_LOCK Disabled (MTR_LOCK_MODE = 11b)
          5. 8.3.16.8.5 75
        9. 8.3.16.9  Thermal Warning (OTW)
        10. 8.3.16.10 Thermal Shutdown (OTSD)
          1. 8.3.16.10.1 OTSD FET
          2. 8.3.16.10.2 OTSD (Non-FET)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
      2. 8.4.2 DRVOFF
    5. 8.5 SPI Communication
      1. 8.5.1 Programming
        1. 8.5.1.1 SPI Format
    6. 8.6 Register Map
      1. 8.6.1 STATUS Registers
      2. 8.6.2 CONTROL Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Hall Sensor Configuration and Connection
      1. 9.2.1 Typical Configuration
      2. 9.2.2 Open Drain Configuration
      3. 9.2.3 Series Configuration
      4. 9.2.4 Parallel Configuration
    3. 9.3 Typical Applications
      1. 9.3.1 Three-Phase Brushless-DC Motor Control With Current Limit
        1. 9.3.1.1 Detailed Design Procedure
          1. 9.3.1.1.1 Motor Voltage
          2. 9.3.1.1.2 Using Active Demagnetization
          3. 9.3.1.1.3 Using Delay Compensation
          4. 9.3.1.1.4 Using the Buck Regulator
          5. 9.3.1.1.5 Power Dissipation and Junction Temperature Losses
        2. 9.3.1.2 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation
  13. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.6.1 STATUS Registers

Table 8-11 lists the memory-mapped registers for the STATUS registers. All register offset addresses not listed in Table 8-11 should be considered as reserved locations and the register contents should not be modified.

Table 8-11 STATUS Registers
OffsetAcronymRegister NameSection
0hIC Status RegisterIC Status RegisterSection 8.6.1.1
1hStatus Register 1Status Register 1Section 8.6.1.2
2hStatus Register 2Status Register 2Section 8.6.1.3

Complex bit access types are encoded to fit into small table cells. Table 8-12 shows the codes that are used for access types in this section.

Table 8-12 STATUS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Reset or Default Value
-nValue after reset or the default value

8.6.1.1 IC Status Register (Offset = 0h) [Reset = 00h]

IC Status Register is shown in Table 8-13.

Return to the Summary Table.

Table 8-13 IC Status Register Field Descriptions
BitFieldTypeResetDescription
7MTR_LOCKR0h Motor Lock Status Bit
0h = No motor lock is detected
1h = Motor lock is detected
6BK_FLTR0h Buck Fault Bit
0h = No buck regulator fault condition is detected
1h = Buck regulator fault condition is detected
5SPI_FLTR0h SPI Fault Bit
0h = No SPI fault condition is detected
1h = SPI Fault condition is detected
4OCPR0h Over Current Protection Status Bit
0h = No overcurrent condition is detected
1h = Overcurrent condition is detected
3NPORR0h Supply Power On Reset Bit
0h = Power on reset condition is detected on VM
1h = No power-on-reset condition is detected on VM
2OVPR0h Supply Overvoltage Protection Status Bit
0h = No overvoltage condition is detected on VM
1h = Overvoltage condition is detected on VM
1OTR0h Overtemperature Fault Status Bit
0h = No overtemperature warning / shutdown is detected
1h = Overtemperature warning / shutdown is detected
0FAULTR0h Device Fault Bit
0h = No fault condition is detected
1h = Fault condition is detected

8.6.1.2 Status Register 1 (Offset = 1h) [Reset = 00h]

Status Register 1 is shown in Table 8-14.

Return to the Summary Table.

Table 8-14 Status Register 1 Field Descriptions
BitFieldTypeResetDescription
7OTWR0h Overtemperature Warning Status Bit
0h = No overtemperature warning is detected
1h = Overtemperature warning is detected
6OTSR0h Overtemperature Shutdown Status Bit
0h = No overtemperature shutdown is detected
1h = Overtemperature shutdown is detected
5OCP_HCR0h Overcurrent Status on High-side switch of OUTC
0h = No overcurrent detected on high-side switch of OUTC
1h = Overcurrent detected on high-side switch of OUTC
4OCL_LCR0h Overcurrent Status on Low-side switch of OUTC
0h = No overcurrent detected on low-side switch of OUTC
1h = Overcurrent detected on low-side switch of OUTC
3OCP_HBR0h Overcurrent Status on High-side switch of OUTB
0h = No overcurrent detected on high-side switch of OUTB
1h = Overcurrent detected on high-side switch of OUTB
2OCP_LBR0h Overcurrent Status on Low-side switch of OUTB
0h = No overcurrent detected on low-side switch of OUTB
1h = Overcurrent detected on low-side switch of OUTB
1OCP_HAR0h Overcurrent Status on High-side switch of OUTA
0h = No overcurrent detected on high-side switch of OUTA
1h = Overcurrent detected on high-side switch of OUTA
0OCP_LAR0h Overcurrent Status on Low-side switch of OUTA
0h = No overcurrent detected on low-side switch of OUTA
1h = Overcurrent detected on low-side switch of OUTA

8.6.1.3 Status Register 2 (Offset = 2h) [Reset = 00h]

Status Register 2 is shown in Table 8-15.

Return to the Summary Table.

Table 8-15 Status Register 2 Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR-00h Reserved
6OTP_ERRR0h One Time Programmability Error
0h = No OTP error is detected
1h = OTP Error is detected
5BUCK_OCPR0h Buck Regulator Overcurrent Status Bit
0h = No buck regulator overcurrent is detected
1h = Buck regulator overcurrent is detected
4BUCK_UVR0h Buck Regulator Undervoltage Status Bit
0h = No buck regulator undervoltage is detected
1h = Buck regulator undervoltage is detected
3VCP_UVR0h Charge Pump Undervoltage Status Bit
0h = No charge pump undervoltage is detected
1h = Charge pump undervoltage is detected
2SPI_PARITYR-00h SPI Parity Error Bit
0h = No SPI parity error is detected
1h = SPI parity error is detected
1SPI_SCLK_FLTR0h SPI Clock Framing Error Bit
0h = No SPI clock framing error is detected
1h = SPI clock framing error is detected
0SPI_ADDR_FLTR0h SPI Address Error Bit
0h = No SPI address fault is detected (due to accessing non-user register)
1h = SPI address fault is detected