JAJSSH6 December 2023 MCT8315Z
PRODUCTION DATA
Table 8-16 lists the memory-mapped registers for the CONTROL registers. All register offset addresses not listed in Table 8-16 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 3h | Control Register 1 | Control Register 1 | Section 8.6.2.1 |
| 4h | Control Register 2 | Control Register 2 | Section 8.6.2.2 |
| 5h | Control Register 3 | Control Register 3 | Section 8.6.2.3 |
| 6h | Control Register 4 | Control Register 4 | Section 8.6.2.4 |
| 7h | Control Register 5 | Control Register 5 | Section 8.6.2.5 |
| 8h | Control Register 6 | Control Register 6 | Section 8.6.2.6 |
| 9h | Control Register 7 | Control Register 7 | Section 8.6.2.7 |
| Ah | Control Register 8 | Control Register 8 | Section 8.6.2.8 |
| Bh | Control Register 9 | Control Register 9 | Section 8.6.2.9 |
| Ch | Control Register 10 | Control Register 10 | Section 8.6.2.10 |
Complex bit access types are encoded to fit into small table cells. Table 8-17 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| R-0 | R -0 | Read Returns 0s |
| Write Type | ||
| W | W | Write |
| W1C | W 1C | Write 1 to clear |
| WAPU | W APU | Write Atomic write with password unlock |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |
Control Register 1 is shown in Table 8-18.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-3 | RESERVED | R-0 | 0h | Reserved |
| 2-0 | REG_LOCK | R/WAPU | 0h | Register Lock Bits
0h = No effect unless locked or unlocked 1h = No effect unless locked or unlocked 2h = No effect unless locked or unlocked 3h = Write 011b to this register to unlock all registers 4h = No effect unless locked or unlocked 5h = No effect unless locked or unlocked 6h = Write 110b to lock the settings by ignoring further register writes except to these bits and address 0x03h bits 2-0. 7h = No effect unless locked or unlocked |
Control Register 2 is shown in Table 8-19.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R/W | 0h | Reserved |
| 5 | SDO_MODE | R/W | 0h | SDO Mode Setting
0h = SDO IO in Open Drain Mode 1h = SDO IO in Push Pull Mode |
| 4-3 | SLEW | R/W | 0h | Slew Rate Settings
0h = Slew rate is 25 V/µs 1h = Slew rate is 50 V/µs 2h = Slew rate is 125 V/µs 3h = Slew rate is 200 V/µs |
| 2-1 | PWM_MODE | R/W | 0h | Device Mode Selection
0h = Asynchronous rectification with analog Hall 1h = Asynchronous rectification with digital Hall 2h = Synchronous rectification with analog Hall 3h = Synchronous rectification with digital Hall |
| 0 | CLR_FLT | W1C | 0h | Clear Fault
0h = No clear fault command is issued 1h = To clear the latched fault bits. This bit automatically resets after being written. |
Control Register 3 is shown in Table 8-20.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R-0 | 0h | Reserved |
| 6 | RESERVED | R/W | 0h | Reserved |
| 5 | RESERVED | R/W | 0h | Reserved |
| 4 | PWM_100_DUTY_SEL | R/W | 0h | Frequency of PWM at 100% Duty Cycle
0h = 20KHz 1h = 40KHz |
| 3 | OVP_SEL | R/W | 0h | Overvoltage Level Setting
0h = VM overvoltage level is 34-V 1h = VM overvoltage level is 22-V |
| 2 | OVP_EN | R/W | 1h | Overvoltage Enable Bit
0h = Overvoltage protection is disabled 1h = Overvoltage protection is enabled |
| 1 | SPI_FLT_REP | R/W | 1h | SPI Fault Reporting Disable Bit
0h = SPI fault reporting on nFAULT pin is enabled 1h = SPI fault reporting on nFAULT pin is disabled |
| 0 | OTW_REP | R/W | 0h | Overtemperature Warning Reporting Bit
0h = Over temperature reporting on nFAULT is disabled 1h = Over temperature reporting on nFAULT is enabled |
Control Register 4 is shown in Table 8-21.
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| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | DRV_OFF | R/W | 0h | Driver OFF Bit
0h = No Action 1h = Hi-Z FETs |
| 6 | OCP_CBC | R/W | 0h | OCP PWM Cycle Operation Bit
0h = OCP clearing in PWM input cycle change is disabled 1h = OCP clearing in PWM input cycle change is enabled |
| 5-4 | OCP_DEG | R/W | 1h | OCP Deglitch Time Settings
0h = OCP deglitch time is 0.2 µs 1h = OCP deglitch time is 0.6 µs 2h = OCP deglitch time is 1.2 µs 3h = OCP deglitch time is 1.6 µs |
| 3 | OCP_RETRY | R/W | 0h | OCP Retry Time Settings
0h = OCP retry time is 5 ms 1h = OCP retry time is 500 ms |
| 2 | OCP_LVL | R/W | 0h | Overcurrent Level Setting
0h = OCP level is 9 A 1h = OCP level is 13 A |
| 1-0 | OCP_MODE | R/W | 0h | OCP Fault Mode
0h = Overcurrent causes a latched fault 1h = Overcurrent causes an automatic retrying fault 2h = Reserved 3h = Reserved |
Control Register 5 is shown in Table 8-22.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R/W | 0h | Reserved |
| 6 | ILIM_RECIR | R/W | 0h | Current Limit Recirculation Settings
0h = Current recirculation through FETs (Brake Mode) 1h = Current recirculation through diodes (Coast Mode) |
| 5 | RESERVED | R/W | 0h | Reserved |
| 4 | RESERVED | R/W | 0h | Reserved |
| 3 | EN_AAR | R/W | 0h | Active Asynchronous Rectification Enable Bit
0h = AAR mode is disabled 1h = AAR mode is enabled |
| 2 | EN_ASR | R/W | 0h | Active Synchronous Rectification Enable Bit
0h = ASR mode is disabled 1h = ASR mode is enabled |
| 1-0 | RESERVED | R/W | 0h | Reserved |
Control Register 6 is shown in Table 8-23.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R-0 | 0h | Reserved |
| 5 | RESERVED | R/W | 0h | Reserved |
| 4 | BUCK_PS_DIS | R/W | 0h | Buck Power Sequencing Disable Bit
0h = Buck power sequencing is enabled 1h = Buck power sequencing is disabled |
| 3 | BUCK_CL | R/W | 0h | Buck Current Limit Setting
0h = Buck regulator current limit is set to 600 mA 1h = Buck regulator current limit is set to 150 mA |
| 2-1 | BUCK_SEL | R/W | 0h | Buck Voltage Selection
0h = Buck voltage is 3.3 V 1h = Buck voltage is 5.0 V 2h = Buck voltage is 4.0 V 3h = Buck voltage is 5.7 V |
| 0 | BUCK_DIS | R/W | 0h | Buck Disable Bit
0h = Buck regulator is enabled 1h = Buck regulator is disabled |
Control Register 7 is shown in Table 8-24.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | RESERVED | R-0 | 0h | Reserved |
| 4 | HALL_HYS | R/W | 0h | Hall Comparator Hysteresis Settings
0h = 5 mV 1h = 50 mV |
| 3 | BRAKE_MODE | R/W | 0h | Brake Mode Setting
0h = Device operation is braking in brake mode 1h = Device operation is coasting in brake mode |
| 2 | COAST | R/W | 0h | Coast Bit
0h = Device coast mode is disabled 1h = Device coast mode is enabled |
| 1 | RESERVED | R/W | 0h | Reserved |
| 0 | DIR | R/W | 0h | Direction Bit
0h = Motor direction is set to clockwise direction 1h = Motor direction is set to anti-clockwise direction |
Control Register 8 is shown in Table 8-25.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | FGOUT_SEL | R/W | 0h | Electrical Frequency Generation Output Mode Bits
0h = FGOUT frequency is 3x commutation frequency 1h = FGOUT frequency is 1x of commutation frequency 2h = FGOUT frequency is 0.5x of commutation frequency 3h = FGOUT frequency is 0.25x of commutation frequency |
| 5 | RESERVED | R-0 | 0h | Reserved |
| 4 | MTR_LOCK_RETRY | R/W | 0h | Motor Lock Retry Time Settings
0h = 500 ms 1h = 5000 ms |
| 3-2 | MTR_LOCK_TDET | R/W | 0h | Motor Lock Detection Time Settings
0h = 300 ms 1h = 500 ms 2h = 1000 ms 3h = 5000 ms |
| 1-0 | MTR_LOCK_MODE | R/W | 0h | Motor Lock Fault Options
0h = Motor lock causes a latched fault 1h = Motor lock causes an automatic retrying fault 2h = Motor lock is report only but no action is taken 3h = Motor lock is not reported and no action is taken |
Control Register 9 is shown in Table 8-26.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-3 | RESERVED | R-0 | 0h | Reserved |
| 2-0 | ADVANCE_LVL | R/W | 0h | Phase Advance Setting
0h = 0° 1h = 4° 2h = 7° 3h = 11° 4h = 15° 5h = 20° 6h = 25° 7h = 30° |
Control Register 10 is shown in Table 8-27.
Return to the Summary Table.
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-5 | RESERVED | R-0 | 0h | Reserved |
| 4 | DLYCMP_EN | R/W | 0h | Driver Delay Compensation enable
0h = Disable 1h = Enable |
| 3-0 | DLY_TARGET | R/W | 0h | Delay Target for Driver Delay Compensation
0h = 0 µs 1h = 0.4 µs 2h = 0.6 µs 3h = 0.8 µs 4h = 1 µs 5h = 1.2 µs 6h = 1.4 µs 7h = 1.6 µs 8h = 1.8 µs 9h = 2 µs Ah = 2.2 µs Bh = 2.4 µs Ch = 2.6 µs Dh = 2.8 µs Eh = 3 µs Fh = 3.2 µs |