JAJSG80B May   2015  – September 2020 MSP430FG6425 , MSP430FG6426 , MSP430FG6625 , MSP430FG6626

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Type
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 8.6 Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    7. 8.7 Thermal Resistance Characteristics
    8. 8.8 Timing and Switching Characteristics
      1. 8.8.1  Power Supply Sequencing
        1. 8.8.1.1 Brownout and Device Reset Power Ramp Requirements
      2. 8.8.2  Reset Timing
        1. 8.8.2.1 Reset Input
      3. 8.8.3  Clock Specifications
        1. 8.8.3.1 Crystal Oscillator, XT1, Low-Frequency Mode
        2. 8.8.3.2 Crystal Oscillator, XT2
        3. 8.8.3.3 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        4. 8.8.3.4 Internal Reference, Low-Frequency Oscillator (REFO)
        5. 8.8.3.5 DCO Frequency
      4. 8.8.4  Wake-up Characteristics
        1. 8.8.4.1 Wake-up Times From Low-Power Modes and Reset
      5. 8.8.5  General-Purpose I/Os
        1. 8.8.5.1 Schmitt-Trigger Inputs – General-Purpose I/O
        2. 8.8.5.2 Inputs – Ports P1, P2, P3, and P4
        3. 8.8.5.3 Leakage Current – General-Purpose I/O
        4. 8.8.5.4 Outputs – General-Purpose I/O (Full Drive Strength)
        5. 8.8.5.5 Outputs – General-Purpose I/O (Reduced Drive Strength)
        6. 8.8.5.6 Output Frequency – Ports P1, P2 and P3
        7. 8.8.5.7 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
        8. 8.8.5.8 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
      6. 8.8.6  PMM
        1. 8.8.6.1 PMM, Core Voltage
        2. 8.8.6.2 PMM, SVS High Side
        3. 8.8.6.3 PMM, SVM High Side
        4. 8.8.6.4 PMM, SVS Low Side
        5. 8.8.6.5 PMM, SVM Low Side
      7. 8.8.7  Timers
        1. 8.8.7.1 Timer_A, Timers TA0, TA1, and TA2
        2. 8.8.7.2 Timer_B, Timer TB0
      8. 8.8.8  Battery Backup
        1. 8.8.8.1 Battery Backup
      9. 8.8.9  USCI
        1. 8.8.9.1 USCI (UART Mode)
        2. 8.8.9.2 USCI (SPI Master Mode)
        3. 8.8.9.3 USCI (SPI Slave Mode)
        4. 8.8.9.4 USCI (I2C Mode)
      10. 8.8.10 LCD Controller
        1. 8.8.10.1 LCD_B Operating Conditions
        2. 8.8.10.2 LCD_B, Electrical Characteristics
      11. 8.8.11 CTSD16
        1. 8.8.11.1 CTSD16, Power Supply and Operating Conditions
        2.       66
        3. 8.8.11.2 CTSD16, External Voltage Reference
        4. 8.8.11.3 CTSD16, Input Range
        5. 8.8.11.4 CTSD16, Performance
        6.       70
        7. 8.8.11.5 Built-in Vcc Sense
        8. 8.8.11.6 Temperature Sensor
      12. 8.8.12 REF
        1. 8.8.12.1 REF and REFBG, Built-In Reference
      13. 8.8.13 DAC
        1. 8.8.13.1 12-Bit DAC, Supply Specifications
        2. 8.8.13.2 12-Bit DAC, Linearity Specifications
        3. 8.8.13.3 12-Bit DAC, Output Specifications
        4. 8.8.13.4 12-Bit DAC, Reference Input Specifications
        5. 8.8.13.5 12-Bit DAC, Dynamic Specifications
        6. 8.8.13.6 12-Bit DAC, Dynamic Specifications (Continued)
      14. 8.8.14 Operational Amplifier
        1. 8.8.14.1 Operational Amplifier, OA0, OA1, PGA Buffers
        2. 8.8.14.2 OA, Current Calculation
      15. 8.8.15 Switches
        1. 8.8.15.1 Ground Switches (GSW0A, GSW0B, GSW1A, GSW1B)
        2. 8.8.15.2 Operational Amplifier Switches
      16. 8.8.16 Comparator
        1. 8.8.16.1 Comparator_B
      17. 8.8.17 USB
        1. 8.8.17.1 Ports PU.0 and PU.1
        2. 8.8.17.2 USB Output Ports DP and DM
        3. 8.8.17.3 USB Input Ports DP and DM
        4. 8.8.17.4 USB-PWR (USB Power System)
        5. 8.8.17.5 USB-PLL (USB Phase-Locked Loop)
      18. 8.8.18 LDO-PWR (LDO Power System)
        1. 8.8.18.1 LDO-PWR (LDO Power System)
      19. 8.8.19 Flash
        1. 8.8.19.1 Flash Memory
      20. 8.8.20 Debug and Emulation
        1. 8.8.20.1 JTAG and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Instruction Set
    4. 9.4  Operating Modes
    5. 9.5  Interrupt Vector Addresses
    6. 9.6  USB BSL
    7. 9.7  UART BSL
    8. 9.8  JTAG Operation
      1. 9.8.1 JTAG Standard Interface
      2. 9.8.2 Spy-Bi-Wire Interface
    9. 9.9  Flash Memory
    10. 9.10 RAM
    11. 9.11 Backup RAM
    12. 9.12 Peripherals
      1. 9.12.1  Digital I/O
      2. 9.12.2  Port Mapping Controller
      3. 9.12.3  Oscillator and System Clock
      4. 9.12.4  Power Management Module (PMM)
      5. 9.12.5  Hardware Multiplier (MPY32)
      6. 9.12.6  Real-Time Clock (RTC_B)
      7. 9.12.7  Watchdog Timer (WDT_A)
      8. 9.12.8  System Module (SYS)
      9. 9.12.9  DMA Controller
      10. 9.12.10 Universal Serial Communication Interface (USCI)
      11. 9.12.11 Timer TA0
      12. 9.12.12 Timer TA1
      13. 9.12.13 Timer TA2
      14. 9.12.14 Timer TB0
      15. 9.12.15 Comparator_B
      16. 9.12.16 Signal Chain
        1. 9.12.16.1 CTSD16
        2. 9.12.16.2 DAC12_A
        3. 9.12.16.3 Operational Amplifiers (OA)
        4. 9.12.16.4 Ground Switches (GSW)
      17. 9.12.17 REF Voltage Reference
      18. 9.12.18 CRC16
      19. 9.12.19 LCD_B
      20. 9.12.20 USB Universal Serial Bus
      21. 9.12.21 LDO and PU Port
      22. 9.12.22 Embedded Emulation Module (EEM) (L Version)
    13. 9.13 Input/Output Diagrams
      1. 9.13.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.13.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.13.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.13.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.13.5  Port P5 (P5.0) Input/Output With Schmitt Trigger
      6. 9.13.6  Port P5 (P5.1 and P5.6) Input/Output With Schmitt Trigger
      7. 9.13.7  Port P5 (P5.3 to P5.5, P5.7) Input/Output With Schmitt Trigger
      8. 9.13.8  Port P6 (P6.0 to P6.1) Input/Output With Schmitt Trigger
      9. 9.13.9  Port P6 (P6.2 and P6.3) Input/Output With Schmitt Trigger
      10. 9.13.10 Port P6 (P6.4) Input/Output With Schmitt Trigger
      11. 9.13.11 Port P6 (P6.5) Input/Output With Schmitt Trigger
      12. 9.13.12 Port P6 (P6.6) Input/Output With Schmitt Trigger
      13. 9.13.13 Port P6 (P6.7) Input/Output With Schmitt Trigger
      14. 9.13.14 Port P7 (P7.2 and P7.3) Input/Output With Schmitt Trigger
      15. 9.13.15 Port P7 (P7.4) Input/Output With Schmitt Trigger
      16. 9.13.16 Port P7 (P7.5) Input/Output With Schmitt Trigger
      17. 9.13.17 Port P7 (P7.6) Input/Output With Schmitt Trigger
      18. 9.13.18 Port P7 (P7.7) Input/Output With Schmitt Trigger
      19. 9.13.19 Port P8 (P8.0 to P8.7) Input/Output With Schmitt Trigger
      20. 9.13.20 Port P9 (P9.0 to P9.7) Input/Output With Schmitt Trigger
      21. 9.13.21 Port U (PU.0/DP, PU.1/DM, PUR) USB Ports for MSP430FG662x
      22. 9.13.22 Port J (J.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      23. 9.13.23 Port J (J.1 to J.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    14. 9.14 Device Descriptors
    15. 9.15 Memory
      1. 9.15.1 Peripheral File Map
    16. 9.16 Identification
      1. 9.16.1 Revision Identification
      2. 9.16.2 Device Identification
      3. 9.16.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 CTSD16 Peripheral
        1. 10.2.1.1 Example Measurement Schematic – Differential Input
        2. 10.2.1.2 Example Measurement Schematic – Single-Ended Input
        3. 10.2.1.3 Design Requirements
        4. 10.2.1.4 Detailed Design Procedure
          1. 10.2.1.4.1 OSR and Sampling Frequency
          2. 10.2.1.4.2 Differential Input Range Explanation
          3. 10.2.1.4.3 Single-Ended Input Mode
          4. 10.2.1.4.4 Offset Calibration
        5. 10.2.1.5 Layout Guidelines
      2. 10.2.2 Operational Amplifier With Ground Switches Peripheral
        1. 10.2.2.1 Reference Schematic
        2. 10.2.2.2 Design Requirements
        3. 10.2.2.3 Detailed Design Procedure
        4. 10.2.2.4 Layout Guidelines
      3. 10.2.3 RTC_B With Battery Backup System
        1. 10.2.3.1 Partial Schematic
        2. 10.2.3.2 Retaining an Accurate Real-Time Clock (RTC) Through Main Supply Interrupts
        3. 10.2.3.3 Charging Super-Capacitors With Built-In Resistive Charger
      4. 10.2.4 LCD_B Peripheral
        1. 10.2.4.1 Partial Schematic
        2. 10.2.4.2 Design Requirements
        3. 10.2.4.3 Detailed Design Procedure
        4. 10.2.4.4 Layout Guidelines
      5. 10.2.5 DAC12 Peripheral
        1. 10.2.5.1 Partial Schematic
        2. 10.2.5.2 Design Requirements
        3. 10.2.5.3 Detailed Design Procedure
        4. 10.2.5.4 Layout Guidelines
      6. 10.2.6 USB Module
      7. 10.2.7 LDO Module
        1. 10.2.7.1 Partial Schematic
  11. 11Device and Documentation Support
    1. 11.1  Getting Started
    2. 11.2  Device Nomenclature
    3. 11.3  Tools and Software
    4. 11.4  Documentation Support
    5. 11.5  Related Links
    6. 11.6  サポート・リソース
    7. 11.7  Trademarks
    8. 11.8  静電気放電に関する注意事項
    9. 11.9  Export Control Notice
    10. 11.10 用語集
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3 Recommended Operating Conditions

Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage during program execution and flash programming (AVCC  =  DVCC1 = DVCC2 = DVCC3  = DVCC = VCC) (1) (2) (3) PMMCOREV = 0 1.8 3.6 V
PMMCOREV = 0, 1 2.0 3.6
PMMCOREV = 0, 1, 2 2.2 3.6
PMMCOREV = 0, 1, 2, 3 2.4 3.6
VCC,USB (2) Supply voltage during USB operation, USB PLL disabled (USB_EN = 1, UPLLEN = 0) PMMCOREV = 0 1.8 3.6 V
PMMCOREV = 0, 1 2.0 3.6
PMMCOREV = 0, 1, 2 2.2 3.6
PMMCOREV = 0, 1, 2, 3 2.4 3.6
Supply voltage during USB operation, USB PLL enabled (4) (USB_EN = 1, UPLLEN = 1) PMMCOREV = 2 2.2 3.6
PMMCOREV = 2, 3 2.4 3.6
VSS Supply voltage (AVSS1 = AVSS2 = AVSS3 = DVSS1 = DVSS2 = DVSS3  =  VSS) 0 V
VBAT,RTC Backup-supply voltage with RTC operational TA = 0°C to 85°C 1.55 3.6 V
TA = –40°C to 85°C 1.70 3.6
VBAT,MEM Backup-supply voltage with backup memory retained TA = –40°C to 85°C 1.20 3.6 V
TA Operating free-air temperature I version –40 85 °C
TJ Operating junction temperature I version –40 85 °C
CBAK Capacitance at pin VBAK 1 4.7 10 nF
CVCORE Capacitor at VCORE(5) 470 nF
CDVCC/ CVCORE Capacitor ratio of DVCC to VCORE 10
fSYSTEM Processor frequency (maximum MCLK frequency) (6) (7) (see Figure 8-1) PMMCOREV = 0,
1.8 V ≤ VCC ≤ 3.6 V (default condition)		 0 8.0 MHz
PMMCOREV = 1,
2 V ≤ VCC ≤ 3.6 V		 0 12.0
PMMCOREV = 2,
2.2 V ≤ VCC ≤ 3.6 V		 0 16.0
PMMCOREV = 3,
2.4 V ≤ VCC ≤ 3.6 V		 0 20.0
fSYSTEM_USB Minimum processor frequency for USB operation 1.5 MHz
USB_wait Wait state cycles during USB operation 16 cycles
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up and operation.
(2) Some modules may have reduced recommended ranges of operation.
(3) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the threshold parameters in Section 8.8.6.2 for the exact values and further details.
(4) USB operation with USB PLL enabled requires PMMCOREV ≥ 2 for proper operation.
(5) A capacitor tolerance of ±20% is required.
(6) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse duration of the specified maximum frequency.
(7) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
GUID-FC5A2055-579D-449F-AB1B-4889B6B960AC-low.gif Figure 8-1 Frequency vs Supply Voltage