JAJSJG6A データシート

JAJSJG6A december 2021 – june 2023 TDP0604

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RNQ|40
- MPQF457A

サーマルパッド・メカニカル・データ

発注情報

8.6.1 TDP0604 Registers

Table 8-19 lists the memory-mapped registers for the TDP0604 registers. All register offset addresses not listed in Table 8-19 should be considered as reserved locations and the register contents should not be modified.

Table 8-19 TDP0604 Registers

Offset	Acronym	Register Name	Section
8h	REV_ID	Revision ID	Go
9h	PD_RST	Power Down and Reset control	Go
Ah	MISC_CONTROL	Misc Control	Go
Bh	GBL_SLEW_CTRL	Global TX Slew control for data lanes in HDMI1.4 and 2.0	Go
Ch	GBL_SLEW_CTRL2	Global TX Slew control for data and clock	Go
Dh	GBL_CTRL1	Global control	Go
Eh	GBL_CTLE_CTRL	Global CTLE control	Go
10h	DDC_CFG	DDC Buffer controls	Go
11h	LANE_ENABLE	Lane enables	Go
12h	CLK_CONFIG1	CLK lane TX swing control	Go
13h	CLK_CONFIG2	CLK lane RX EQ control	Go
14h	D0_CONFIG1	D0 lane TX swing and FFE control	Go
15h	D0_CONFIG2	D0 lane RX EQ control	Go
16h	D1_CONFIG1	D1 lane TX swing and FFE control	Go
17h	D1_CONFIG2	D1 lane RX EQ control	Go
18h	D2_CONFIG1	D2 lane TX swing and FFE control	Go
19h	D2_CONFIG2	D2 lane RX EQ control	Go
1Ah	SIGDET_TH_CFG	SIGDET voltage threshold control	Go
1Ch	GBL_STATUS	Global Powerdown and Standby Status	Go
20h	SCDC_TMDS_CONFIG	SCDC TMDS Clock Ratio	Go
31h	DP_MODE_CONFIG	Selects between DP and HDMI.	Go

Complex bit access types are encoded to fit into small table cells. Table 8-20 shows the codes that are used for access types in this section.

Table 8-20 TDP0604 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
RH	R H	Read Set or cleared by hardware
Write Type
W	W	Write
W1S	W 1S	Write 1 to set
WtoPH	W toPH	Write Pulse high
Reset or Default Value
-n		Value after reset or the default value

8.6.1.1 REV_ID Register (Offset = 8h) [Reset = 03h]

REV_ID is shown in Table 8-21.

Return to the Summary Table.

Table 8-21 REV_ID Register Field Descriptions

Bit	Field	Type	Reset	Description
7-0	REV_ID	RH	3h	Device revision.

8.6.1.2 PD_RST Register (Offset = 9h) [Reset = 01h]

PD_RST is shown in Table 8-22.

Return to the Summary Table.

Table 8-22 PD_RST Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SOFT_RST	WtoPH	0h	Writing a 1 to this field resets all fields
6	SCDC_SOFT_RST	WtoPH	0h	Writing a 1 to this field resets the SCDC register 20h.
5	RESERVED	R	0h	Reserved
4	RESERVED	R/W	0h	Reserved
3	RESERVED	R	0h	Reserved
2	HPD_PWRDWN_DISABLE	R/W	0h	Mode to ignore HPD pin and always enter active state unless PD_EN is high 0h = Automatically enter power down based on HPD_IN 1h = Always remain in active state or Standby
1	STANDBY_DISABLE	R/W	0h	When high, standby mode is disabled and the device will immediately enter active mode with all lanes enabled when not in power down. When low, the device will enter standby mode when exiting power down and wait for incoming data before entering active mode. 0h = Standby mode enabled 1h = Standby mode disabled
0	PD_EN	R/W	1h	I2C power down. Software should clear this field after it has completed initialization. HPD_OUT will be asserted low when this field is set. 0h = Normal operation 1h = Forced power down by I2C

8.6.1.3 MISC_CONTROL Register (Offset = Ah) [Reset = 08h]

MISC_CONTROL is shown in Table 8-23.

Return to the Summary Table.

Table 8-23 MISC_CONTROL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	LANE_SWAP	R/W	0h	This field swaps the input and output lanes. 0h = No lanes swapped 1h = Both input and output lanes swapped
6	RESERVED	R/W	0h	Reserved
5	RX_TERM_DISABLE	R/W	0h	When set will disable Rx termination. 0h = Enabled when HPD_IN high. 1h = Disable
4	HPD_OUT_SEL	R/W	0h	Selects whether HPD_OUT is push/pull or open-drain. 0h = Push Pull 1h = Open Drain
3	RESERVED	R/W	1h	Reserved
2	RATE_SNOOP_CTRL	R/W	0h	Control snooping of HDMI rates. When snooping is disabled, correct HDMI rate must be written through I2C to register 20h. 0h = Snooping enabled 1h = Snooping disabled
1-0	RESERVED	R/W	0h	Reserved

8.6.1.4 GBL_SLEW_CTRL Register (Offset = Bh) [Reset = 34h]

GBL_SLEW_CTRL is shown in Table 8-24.

Return to the Summary Table.

Table 8-24 GBL_SLEW_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6-4	SLEW_3G	R/W	3h	Field controls slew rate for HDMI 1.4 data lane. 0h = slowest edge rate 7h = fastest edge rate
3	RESERVED	R	0h	Reserved
2-0	SLEW_6G	R/W	4h	Field controls slew rate for HDMI 2.0 data lanes. 0h = slowest edge rate 7h = fastest edge rate

8.6.1.5 GBL_SLEW_CTRL2 Register (Offset = Ch) [Reset = 71h]

GBL_SLEW_CTRL2 is shown in Table 8-25.

Return to the Summary Table.

Table 8-25 GBL_SLEW_CTRL2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6-4	RESERVED	R/W	7h	Reserved
3	RESERVED	R	0h	Reserved
2-0	SLEW_CLK	R/W	1h	Field control slew rate of clock lane. 0h = slowest edge rate 7h = fastest edge rate

8.6.1.6 GBL_CTRL1 Register (Offset = Dh) [Reset = 22h]

GBL_CTRL1 is shown in Table 8-26.

Return to the Summary Table.

Table 8-26 GBL_CTRL1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	GLOBAL_LINR_EN	R/W	0h	Global control for selecting between linear redriver or limited redriver. 0h = Limited 1h = Linear
6	TX_AC_EN	R/W	0h	Controls selection of ac-coupled or dc-coupled TX termination. When AC-coupled is enabled, 50 Ω termination on both P and N to VCC will be enabled. 0h = dc-coupled 1h = ac-coupled
5-4	GLOBAL_DCG	R/W	2h	CTLE DCGain for all lane. 0h = -3 dB 1h = -3 dB 2h = 0 dB 3h = +1 dB
3	TXTERM_AUTO_HDMI14	R/W	0h	Selects between no termination and 300 Ωs when TERM = 2h and operating in HDMI1.4. 0h = No termination for clock less than or equal to 165MHz and 300 Ω for clock greater than 225MHz 1h = 300 Ω
2	CTLEBYP_EN	R/W	0h	Selects whether or not CTLE bypass is enabled or not when GLOBAL_DCG is set to 2h and EQ set to 0h. 0h = CTLE bypass disabled 1h = CTLE bypass enabled
1-0	TERM	R/W	2h	TX termination control 0h = No termination 1h = 300 Ω 2h = Automatic based HDMI mode 3h = 100 Ω

8.6.1.7 GBL_CTLE_CTRL Register (Offset = Eh) [Reset = 3Fh]

GBL_CTLE_CTRL is shown in Table 8-27.

Return to the Summary Table.

Table 8-27 GBL_CTLE_CTRL Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	RESERVED	R/W	0h	Reserved
5-4	HDMI14_CTLE_SEL	R/W	3h	Selects the CTLE used when datarate is HDMI 1.4. Value programmed into this field will apply to data lanes only. Clock lane will always use 3Gbps CTLE. 0h = 3 Gbps CTLE 1h = 6 Gbps CTLE 2h = Auto select based on snoop datarate 3h = Reserved
3-2	HDMI20_CTLE_SEL	R/W	3h	Selects the CTLE used when datarate is HDMI 2.0. Value programmed into this field will apply to data lanes only. Clock lane will always use 3Gbps CTLE. 0h = 3 Gbps CTLE 1h = 6 Gbps CTLE 2h = Auto select based on snoop datarate 3h = Reserved
1-0	RESERVED	R/W	3h	Reserved

8.6.1.8 DDC_CFG Register (Offset = 10h) [Reset = 02h]

DDC_CFG is shown in Table 8-28.

Return to the Summary Table.

Table 8-28 DDC_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h	Reserved
1	DDC_LV_DCC_EN	R/W	1h	Controls whether duty cycle correction is enabled for DDC LV side. 0h = DCC disabled 1h = DCC enabled
0	DDCBUF_EN	R/W	0h	Controls whether or not DDC buffer is enabled. Regardless of the state of this field, the device will always disable the DDC buffer anytime HPD_IN is low or when PD_EN field is 1. 0h = DDC Buffer Disabled 1h = DDC Buffer Enabled

8.6.1.9 LANE_ENABLE Register (Offset = 11h) [Reset = 5Fh]

LANE_ENABLE is shown in Table 8-29.

Return to the Summary Table.

Table 8-29 LANE_ENABLE Register Field Descriptions

Bit	Field	Type	Reset	Description
7-6	HDMI20_VOD	R/W	1h	VOD control for limited redriver in HDMI 2.0 0h = Use values in CLK_VOD, D0_VOD, D1_VOD and D2_VOD 1h = Default (1000 mV) 2h = Default - 5% 3h = Default + 5%
5-4	HDMI14_VOD	R/W	1h	VOD control for limited redriver in HDMI 1.4 0h = Use values in CLK_VOD, D0_VOD, D1_VOD and D2_VOD 1h = Default (1000 mV) 2h = Default - 5% 3h = Default - 10%
3	CLK_LANE_EN	R/W	1h	Enable for CLK lane 0h = Disabled 1h = Enabled
2	D0_LANE_EN	R/W	1h	Enable for D0 lane 0h = Disabled 1h = Enabled
1	D1_LANE_EN	R/W	1h	Enable for D0 lane 0h = Disabled 1h = Enabled
0	D2_LANE_EN	R/W	1h	Enable for D0 lane 0h = Disabled 1h = Enabled

8.6.1.10 CLK_CONFIG1 Register (Offset = 12h) [Reset = 03h]

CLK_CONFIG1 is shown in Table 8-30.

Return to the Summary Table.

Table 8-30 CLK_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6-4	RESERVED	R/W	0h	Reserved
3	RESERVED	R	0h	Reserved
2-0	CLK_VOD	R/W	3h	Differential Swing control for CLK lane. 0h = Limited -15% Linear 800mV 1h = Limited -10% Linear 900mV 2h = Limited - 5% Linear 1000mV 3h = Limited 800mV Linear 1200mV 4h = Limited +5% Linear Reserved 5h = Limited +10% Linear Reserved 6h = Limited +15% Linear Reserved 7h = Limited +20% Linear Reserved

8.6.1.11 CLK_CONFIG2 Register (Offset = 13h) [Reset = 00h]

CLK_CONFIG2 is shown in Table 8-31.

Return to the Summary Table.

Table 8-31 CLK_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3-0	CLK_EQ	R/W	0h	EQ control for CLK lane. This field is only honored in DisplayPort mode. 0h = Min EQ Fh = Max EQ

8.6.1.12 D0_CONFIG1 Register (Offset = 14h) [Reset = 03h]

D0_CONFIG1 is shown in Table 8-32.

Return to the Summary Table.

Table 8-32 D0_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6-4	D0_TXFFE	R/W	0h	TXFFE control for D0 lane. 0h = 0.0 dB 1h = 3.5 dB 2h = 6.0 dB 3h = Reserved 4h = -1.5 dB 5h = -2.5 dB 6h = -3.5 dB 7h = -4.8 dB
3	RESERVED	R	0h	Reserved
2-0	D0_VOD	R/W	3h	Differential Swing control for D0 lane. 0h = Limited -15% Linear 800mV 1h = Limited -10% Linear 900mV 2h = Limited - 5% Linear 1000mV 3h = Limited 1000mV Linear 1200mV 4h = Limited +5% Linear Reserved 5h = Limited +10% Linear Reserved 6h = Limited +15% Linear Reserved 7h = Limited +20% Linear Reserved

8.6.1.13 D0_CONFIG2 Register (Offset = 15h) [Reset = 00h]

D0_CONFIG2 is shown in Table 8-33.

Return to the Summary Table.

Table 8-33 D0_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3-0	D0_EQ	R/W	0h	EQ control for D0 lane. 0h = Min EQ Fh = Max EQ

8.6.1.14 D1_CONFIG1 Register (Offset = 16h) [Reset = 03h]

D1_CONFIG1 is shown in Table 8-34.

Return to the Summary Table.

Table 8-34 D1_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6-4	D1_TXFFE	R/W	0h	TXFFE control for D1 lane. 0h = 0.0 dB 1h = 3.5 dB 2h = 6.0 dB 3h = Reserved 4h = -1.5 dB 5h = -2.5 dB 6h = -3.5 dB 7h = -4.8 dB
3	RESERVED	R	0h	Reserved
2-0	D1_VOD	R/W	3h	Differential Swing control for D1 lane. 0h = Limited -15% Linear 800mV 1h = Limited -10% Linear 900mV 2h = Limited - 5% Linear 1000mV 3h = Limited 1000mV Linear 1200mV 4h = Limited +5% Linear Reserved 5h = Limited +10% Linear Reserved 6h = Limited +15% Linear Reserved 7h = Limited +20% Linear Reserved

8.6.1.15 D1_CONFIG2 Register (Offset = 17h) [Reset = 00h]

D1_CONFIG2 is shown in Table 8-35.

Return to the Summary Table.

Table 8-35 D1_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3-0	D1_EQ	R/W	0h	EQ control for D1 lane 0h = Min EQ Fh = Max EQ

8.6.1.16 D2_CONFIG1 Register (Offset = 18h) [Reset = 03h]

D2_CONFIG1 is shown in Table 8-36.

Return to the Summary Table.

Table 8-36 D2_CONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6-4	D2_TXFFE	R/W	0h	TXFFE control for D2 lane 0h = 0.0 dB 1h = 3.5 dB 2h = 6.0 dB 3h = Reserved 4h = -1.5 dB 5h = -2.5 dB 6h = -3.5 dB 7h = -4.8 dB
3	RESERVED	R	0h	Reserved
2-0	D2_VOD	R/W	3h	Differential Swing control for D2 lane. 0h = Limited -15% Linear 800mV 1h = Limited -10% Linear 900mV 2h = Limited - 5% Linear 1000mV 3h = Limited 1000mV Linear 1200mV 4h = Limited +5% Linear Reserved 5h = Limited +10% Linear Reserved 6h = Limited +15% Linear Reserved 7h = Limited +20% Linear Reserved

8.6.1.17 D2_CONFIG2 Register (Offset = 19h) [Reset = 00h]

D2_CONFIG2 is shown in Table 8-37.

Return to the Summary Table.

Table 8-37 D2_CONFIG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	R	0h	Reserved
3-0	D2_EQ	R/W	0h	EQ control for D2 lane. 0h = Min EQ Fh = Max EQ

8.6.1.18 SIGDET_TH_CFG Register (Offset = 1Ah) [Reset = 44h]

SIGDET_TH_CFG is shown in Table 8-38.

Return to the Summary Table.

Table 8-38 SIGDET_TH_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6-4	CFG_SIGDET_HYST	R/W	4h	Controls the SIGDET hysteresis. Value programmed into this field plus value programmed into CFG_SIGDET_VTH field defines the SIGDET assert threshold. 0h = 0mV 1h = 12mV 2h = 25mV 3h = 37mV 4h = 55mV 5h = 63mV 6h = 75mV 7h = 90mV
3	RESERVED	R	0h	Reserved
2-0	CFG_SIGDET_VTH	R/W	4h	Controls the SIGDET de-assert voltage threshold. 0h = 58mV 1h = 60mV 2h = 72mV 3h = 84mV 4h = 95mV 5h = 108mV 6h = 120mV 7h = 135mV

8.6.1.19 GBL_STATUS Register (Offset = 1Ch) [Reset = 00h]

GBL_STATUS is shown in Table 8-39.

Return to the Summary Table.

Table 8-39 GBL_STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
7	PD_STATUS	RH	0h	Power Down status
6	STANDBY_STATUS	RH	0h	Standby Status
5-0	RESERVED	R	0h	Reserved

8.6.1.20 SCDC_TMDS_CONFIG Register (Offset = 20h) [Reset = 00h]

SCDC_TMDS_CONFIG is shown in Table 8-40.

Return to the Summary Table.

Table 8-40 SCDC_TMDS_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-2	RESERVED	R	0h	Reserved
1	TMDS_CLK_RATIO	RH/W	0h	TMDS Bit Period to TMDS Clock Period Ratio. Reads last value snooped through DDC read/write or I2C write. 0h = 1/10 (HDMI 1.4b) 1h = 1/40 (HDMI 2.0)
0	RESERVED	R	0h	Reserved

8.6.1.21 DP_MODE_CONFIG Register (Offset = 31h) [Reset = 00h]

DP_MODE_CONFIG is shown in Table 8-41.

Return to the Summary Table.

Table 8-41 DP_MODE_CONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
7-4	RESERVED	RH/W	0h	Reserved
3-0	DP_MODE	RH/W	0h	Selects between HDMI and DisplayPort. When enable DisplayPort, software should also enable linear mode. 0h = DisplayPort mode disabled 3h = DisplayPort mode enabled