For the TDP0604 on a high-K board, it is required to solder the PowerPAD™ onto the thermal land to ground. A thermal land is the area of solder-tinned-copper underneath the PowerPAD package. On a high-K board, the TDP0604 can operate over the full temperature range by soldering the PowerPAD onto the thermal land. For the device to operate across the temperature range on a low-K board, a 1-oz Cu trace connecting the GND pins to the thermal land must be used. A simulation shows R_θJA = 30.9°C/W allowing 950-mW power dissipation at 70°C ambient temperature. For information about a general PCB design guide for PowerPAD packages, refer to the PowerPAD Thermally Enhanced Package application report. TI recommends using a four layer stack up at a minimum to accomplish a low-EMI PCB design. TI recommends four layers as the TDP0604 is a single voltage rail device.

• Routing the high-speed TMDS traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects from the HDMI connectors to the Redriver inputs and outputs. It is important to match the electrical length of these high speed traces to minimize both inter-pair and intra-pair skew.
• Placing a solid ground plane next to the high-speed single layer establishes controlled impedance for transmission link interconnects and provides an excellent low-inductance path for the return current flow.
• Placing a power plane next to the ground plane creates an additional high-frequency bypass capacitance.
• Routing slower seed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.
• If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep symmetry. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high frequency bypass capacitance significantly.
• To minimize crosstalk between adjacent differential pairs, the distance between the differential pairs should be at least five times longer than the trace width (5W rule). For the clock differential pair, the distance should be increased to 8W or 10W.

Figure 9-10 Recommended 4 or 6-Layer PCB Stack