JAJSJG6A december 2021 – june 2023 TDP0604
PRODUCTION DATA
The equalizer is used to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board traces or cables. TDP0604 supports fixed receiver equalizer by setting the EQ0 and EQ1 pins or through I2C register.
The TDP0604 has two sets of CTLE curves (3 Gbps CTLE and 6 Gbps CTLE) with each curve having 16 ac gain settings and 3 dc gain settings. The 16 ac gain settings with GLOBAL_DCG = 0x2 is detailed in Table 8-5.
The TDP0604 in pin-strap mode has two CTLE HDMI Datarate Maps: Map B and Map C. These maps are detailed in Table 8-6. The expectation is Map B or C should be used if TDP0604 is used in a source application and Map B for a sink application.
When the TDP0604 is configured for pin-strap mode, the default CTLE HDMI data rate map will be determined by the sampled state of the CTLEMAP_SEL pin as detailed in Table 8-7.
In the I2C mode, the default CTLE (3 Gbps or 6 Gbps) used for each HDMI mode can be controlled from a register.
| EQ Setting(1) | RX EQ Level for 3Gbps CTLE (Gain at 1.5 GHz - Gain at 10 MHz) |
RX EQ Level for 6Gbps CTLE (Gain at 3 GHz - Gain at 10 MHz) |
EQ1 PIN | EQ0 PIN |
|---|---|---|---|---|
| 0(2) | 1.0 | 0.5 | 0 | 0 |
| 1 | 2.0 | 1.0 | 0 | R |
| 2 | 3.2 | 2.4 | 0 | F |
| 3 | 4.2 | 3.3 | 0 | 1 |
| 4 | 5.3 | 4.4 | R | 0 |
| 5 | 6.0 | 5.2 | R | R |
| 6 | 7.0 | 6.0 | R | F |
| 7 | 7.7 | 6.8 | R | 1 |
| 8 | 9.0 | 7.5 | F | 0 |
| 9 | 9.5 | 8.2 | F | R |
| 10 | 10.0 | 8.8 | F | F |
| 11 | 10.5 | 9.3 | F | 1 |
| 12 | 11.0 | 10.0 | 1 | 0 |
| 13 | 11.5 | 10.5 | 1 | R |
| 14 | 12.0 | 11.0 | 1 | F |
| 15 | 12.3 | 11.8 | 1 | 1 |
| HDMI Mode |
Map B |
Map C |
|---|---|---|
| 1.4 |
3 Gbps CTLE |
6 Gbps CTLE |
| 2.0 |
6 Gbps CTLE |
6 Gbps CTLE |
| Sampled State of CTLEMAP_SEL Pin | ||||
|---|---|---|---|---|
| "0" | "R" | "F" | "1" | |
| CTLE HDMI Datarate Map | Reserved |
Map C |
Reserved | Map B |