JAJSJG6A december 2021 – june 2023 TDP0604
PRODUCTION DATA
The HDMI specification limits the DDC bus capacitance to ≤ 50-pF for both an HDMI source and sink. Therefore, care must be taken to make sure the total capacitance of all components (TDP0604, FR4 trace, ESD, source, and sink) is less than 50-pF.
The TDP0604s DDC Buffer offers capacitance isolation between the LV DDC pins and the HV DDC pin. The total capacitance of components, including the FR4 trace, between the TDP0604 HV_DDC_SDA/SCL pins and the HDMI receptacle must be ≤ (50-pF – CIOHV).
If implementing a DDC level shifter using pass gates, then the total capacitance will include all components between source or sink and the HDMI receptacle. These components include and are not limited to Source or Sink, the FR4 trace, ESD components, and TDP0604.