JAJSJG6A december   2021  – june 2023 TDP0604

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  4-Level Inputs
      2. 8.3.2  I/O Voltage Level Selection
      3. 8.3.3  HPD_OUT
      4. 8.3.4  Lane Control
      5. 8.3.5  Swap
      6. 8.3.6  Linear and Limited Redriver
      7. 8.3.7  Main Link Inputs
      8. 8.3.8  Receiver Equalizer
      9. 8.3.9  CTLE Bypass
      10. 8.3.10 Input Signal Detect
      11. 8.3.11 Main Link Outputs
        1. 8.3.11.1 Transmitter Bias
        2. 8.3.11.2 Transmitter Impedance Control
        3. 8.3.11.3 TX Slew Rate Control
        4. 8.3.11.4 TX Pre-Emphasis and De-Emphasis Control
        5. 8.3.11.5 TX Swing Control
      12. 8.3.12 DDC Buffer
      13. 8.3.13 HDMI DDC Capacitance
      14. 8.3.14 DisplayPort
    4. 8.4 Device Functional Modes
      1. 8.4.1 MODE Control
        1. 8.4.1.1 I2C Mode (MODE = "F")
        2. 8.4.1.2 Pin Strap Modes
          1. 8.4.1.2.1 Pin-Strap: HDMI 1.4 and HDMI 2.0 Functional Description
      2. 8.4.2 DDC Snoop Feature
        1. 8.4.2.1 HDMI Type
      3. 8.4.3 Low Power Modes
    5. 8.5 Programming
      1. 8.5.1 Pseudocode Examples
        1. 8.5.1.1 HDMI 2.0 Source Example with DDC Snoop and DDC Buffer Enabled
      2. 8.5.2 TDP0604 I2C Address Options
      3. 8.5.3 I2C Target Behavior
    6. 8.6 Register Maps
      1. 8.6.1 TDP0604 Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Source-Side Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Pre-Channel (LAB)
        2. 9.2.2.2 Post-Channel (LCD)
        3. 9.2.2.3 Common Mode Choke
        4. 9.2.2.4 ESD Protection
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-83311A4D-E43C-4B24-936B-5DFED16CA78E-low.gif Figure 5-1 RNQ Package, 40-Pin WQFN (Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
VCC 1 P 3.3-V power supply
HPDOUT_SEL 2 I
2-Level (PD)		 HPDOUT_SEL. Selects whether HPD_OUT pin is push/pull, or open-drain. Open-drain is not supported in pin-strap mode. Therefore this pin should be left floating or pull-down to GND.
TEST1 3 O Test1. For internal Texas Instruments use only. This pin can be left unconnected.
CTLEMAP_SEL 4 I
4-Level (PU/PD)		 CTLE Map select. When TDP0604 is configured in pin-strap mode, this pin selects the CTLE Map used. Table 8-7 provides more details. In I2C mode, CTLE map is determined by registers.
LINEAR_EN 5 I
4-Level (PU/PD)		 In pin-strap mode, selects whether TDP0604 operates in linear or limited redriver mode. Table 8-4 provides more details.
VCC 6 P 3.3-V power supply.
EN 7 I
2-Level (PU)		 When low, TDP0604 will be held in reset. The IN_D[2:0], IN_CLK, OUT_D[2:0] and OUT_CLK pins will be held in high impedance while EN is low. On rising edge of EN, device will sample 4-level inputs and function based on the sampled state of the pins. This pin has a internal 250k pull-up to VIO.
EQ1 8 I
4 Level (PU/PD)		 EQ1 pin setting when TDP0604 is configured for pin strap mode; Works in conjunction with EQ0; Table 8-5 provides the settings. In I2C mode, EQ settings are controlled through the registers.
IN_D2p 9 I Channel 2 differential positive input.
IN_D2n 10 I Channel 2 differential negative input.
HPD_OUT 11 O Hot plug detect output to source side. If not used, then this pin can be left floating. If used, then it is recommended to have a external 220k resistor to GND on this pin.
IN_D1p 12 I Channel 1 differential positive input.
IN_D1n 13 I Channel 1 differential negative input.
VIO 14 P Voltage supply for I/Os. Table 8-2 provides more details.
IN_D0p 15 I Channel 0 differential positive input.
IN_D0n 16 I Channel 0 differential negative input.
MODE 17 I
4-Level (PU/PD)		 Mode control pin. Selects between pin-strap and I2C mode. Refer to Section 8.4.1.
IN_CLKp 18 I Clock differential positive input.
IN_CLKn 19 I Clock differential negative input.
VCC 20 P 3.3-V power supply.
SCL/CFG0 21 I I2C Clock/CFG0: When TDP0604 is configured for I2C mode, this pin will function as the I2C clock. Otherwise, this pin will function as CFG0 as provided in Table 8-13.
SDA/CFG1 22 I/O I2C Data / CFG1: When TDP0604 is configured for I2C mode, this pin will function as the I2C clock. Otherwise, this pin will function as CFG1 as provided in Table 8-14.
AC_EN 23 I
2-Level (PD)		 In pin-strap mode, selects whether high speed transmitters are externally AC or DC-coupled.
0: DC-coupled
1: AC-coupled
LV_DDC_SCL 24 I/O Low voltage side bidirectional DDC clock line. Internally pulled-up to VIO.
LV_DDC_SDA 25 I/O Low voltage side bidirectional DDC data line. Internally pulled-up to VIO.
HV_DDC_SDA 26 I/O High voltage side bidirectional DDC data line. Pull-up externally to HDMI 5 V.
HV_DDC_SCL 27 I/O High voltage side bidirectional DDC clock line. Pull-up externally to HDMI 5 V.
VCC 28 P 3.3-V power supply.
TXPRE 29 I
4-Level (PU/PD)		 TX pre-emphasis control: In pin-strap mode with limited enabled, this pin controls TX EQ. Table 8-11 provides the available TXPRE settings when operating in pin strap mode. In I2C mode, TX pre-emphasis is controlled through the registers.
OUT_CLKn 30 O TMDS data clock differential negative output
OUT_CLKp 31 O TMDS data clock differential positive output
HPD_IN 32 I
2-Level (PD)		 Hot plug detect input from sink side. This pin has an internal pull-down resistor and is fail-safe.
OUT_D0n 33 O TMDS data 0 differential negative output
OUT_D0p 34 O TMDS data 0 differential positive output
ADDR/EQ0 35 I
4-Level (PU/PD)		 Address bit for I2C programming when TDP0604 is configured for I2C mode. Table 8-18 provides more information.
EQ0 pin setting when TDP0604 is configured for pin strap mode; works in conjunction with EQ1; Table 8-5 provides the settings. In I2C mode, EQ settings are controlled through the registers.
OUT_D1n 36 O TMDS data 1 differential negative output
OUT_D1p 37 O TMDS data 1 differential positive output
TXSWG 38 I
4-Level (PU/PD)		 TX output swing control: 4 settings. This pin is only used in pin strap mode. Table 8-12 provides the available TX swing settings. In I2C mode, TX output swing is controlled through the registers.
OUT_D2n 39 O TMDS data 2 differential negative output
OUT_D2p 40 O TMDS data 2 differential positive output
Thermal Pad 41 GND Thermal pad. Connect to a solid ground plane.
(1) I = input, O = output, GND = ground, P = power, PU = pull-up, PD = pull-down