JAJSOY7A June 2008 – September 2023 TPS2551-Q1
PRODUCTION DATA
The circuit in Figure 9-4 uses an SN74HC00 quad-NAND gate to implement overcurrent latch-off. The SN74HC00 high-speed CMOS logic gate is selected because it operates over the 2.5-V to 6.5-V range of the TPS2551.
This circuit is designed to work with the active-high TPS2551. ENABLE must be logic low during start-up until VIN is stable to ensure that the switch initializes in the OFF state. A logic high on ENABLE turns on the switch after VIN is stable. FAULT momentarily pulls low during an overcurrent condition, which latches STAT logic low and disables the switch. The host can monitor STAT for an overcurrent condition. Toggling ENABLE resets STAT and re-enables the switch.