JAJSNA0 December   2022 TPS25762-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Recommended Components
    5. 7.5  Thermal Information
    6. 7.6  Buck-Boost Regulator
    7. 7.7  CC Cable Detection Parameters
    8. 7.8  CC VCONN Parameters
    9. 7.9  CC PHY Parameters
    10. 7.10 Thermal Shutdown Characteristics
    11. 7.11 Oscillator Characteristics
    12. 7.12 ADC Characteristics
    13. 7.13 TVS Parameters
    14. 7.14 Input/Output (I/O) Characteristics
    15. 7.15 BC1.2 Characteristics
    16. 7.16 I2C Requirements and Characteristics
    17. 7.17 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Device Power Management and Supervisory Circuitry
        1. 9.3.1.1 VIN UVLO and Enable/UVLO
        2. 9.3.1.2 Internal LDO Regulators
      2. 9.3.2  TVSP Device Configuration and ESD Protection
      3. 9.3.3  Buck-Boost Regulator
        1. 9.3.3.1  Buck-Boost Regulator Operation
        2. 9.3.3.2  Switching Frequency, Frequency Dither, Phase-Shift and Synchronization
        3. 9.3.3.3  VIN Supply and VIN Over-Voltage Protection
        4. 9.3.3.4  Feedback Paths and Error Amplifiers
        5. 9.3.3.5  Transconductors and Compensation
        6. 9.3.3.6  Output Voltage DAC, Soft-Start and Cable Droop Compensation
        7. 9.3.3.7  VBUS Overvoltage Protection
        8. 9.3.3.8  VBUS Undervoltage Protection
        9. 9.3.3.9  Current Sense Resistor (RSNS) and Current Limit Operation
        10. 9.3.3.10 Buck-Boost Peak Current Limits
      4. 9.3.4  USB-PD Physical Layer
        1. 9.3.4.1 USB-PD Encoding and Signaling
        2. 9.3.4.2 USB-PD Bi-Phase Marked Coding
        3. 9.3.4.3 USB-PD Transmit (TX) and Receive (Rx) Masks
        4. 9.3.4.4 USB-PD BMC Transmitter
        5. 9.3.4.5 USB-PD BMC Receiver
        6. 9.3.4.6 Squelch Receiver
      5. 9.3.5  VCONN
      6. 9.3.6  Cable Plug and Orientation Detection
        1. 9.3.6.1 Configured as a Source
        2. 9.3.6.2 Configured as a Sink
        3. 9.3.6.3 Overvoltage Protection (Px_CC1, Px_CC2)
      7. 9.3.7  ADC
        1. 9.3.7.1 ADC Divider Ratios
      8. 9.3.8  BC 1.2, Legacy and Fast Charging Modes (Px_DP, Px_DM)
      9. 9.3.9  USB2.0 Low-Speed Endpoint
      10. 9.3.10 Digital Interfaces
        1. 9.3.10.1 General GPIO
        2. 9.3.10.2 I2C Buffer
      11. 9.3.11 I2C Interface
        1. 9.3.11.1 I2C Interface Description
        2. 9.3.11.2 I2C Clock Stretching
        3. 9.3.11.3 I2C Address Setting
        4. 9.3.11.4 Unique Address Interface
        5. 9.3.11.5 I2C Pullup Resistor Calculation
      12. 9.3.12 Digital Core
        1. 9.3.12.1 Device Memory
        2. 9.3.12.2 Core Microprocessor
      13. 9.3.13 NTC Input
      14. 9.3.14 Thermal Sensors and Thermal Shutdown
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Application GUI Selections
        2. 10.2.2.2 EEPROM Selection
        3. 10.2.2.3 EN/UVLO
        4. 10.2.2.4 Sense Resistor, RSNS, RCSP, RCSN and CFILT
        5. 10.2.2.5 Inductor Currents
        6. 10.2.2.6 Output Capacitor
        7. 10.2.2.7 Input Capacitor
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3.1.2 Internal LDO Regulators

Three internal LDOs provide regulated supplies for operation of internal circuitry.

  • LDO_5V: Supplies buck-boost gate drive circuitry, LDO_3V3, LDO_1V5, and PA and PB VCONN power paths. External bypass capacitance, CLDO_5V is required for proper operation. It is highly recommended to include an additional high frequency 0.1 μF capacitor in parallel with CLDO_5V. CLDO_5V and the parallel high frequency should be placed as close to the LDO_5V pin as possible. This capacitance: 1) provides energy storage for the buck-boost internal FET gate drivers, and 2) is required to stabilize the internal 5-V LDO in applications where an external 5-V supply is not connected. The TPS25762-Q1 will not operate (release reset) until VLDO_5V(UVLO_R) threshold is met. Hard reset occurs when VLDO_5V < VLDO_5V(UVLO_F) threshold. Current from LDO_5V returns to PGND pin. The LDO_5V output may be used to supply a small external loads such as indicator LEDs. When supplying external components, it is recommended that the total external load current not exceed 25 mA (MAX).
    • 0.1W VCONN: when enabled in the application configuration GUI, LDO_5V is capable of sourcing 20 mA each to PA_VCONN and PB_VCONN.
    • 1W VCONN: when enabled in the application configuration GUI, this mode of operation requires an external 4.75 - 5.5 V, 500-mA capable supply connected to LDO_5V. Back-feeding of LDO_5V is allowed.
  • LDO_3V3: Supplies internal analog circuits, GPIO buffers, USB PD and the USB Endpoint PHYs. External bypass capacitance of CLDO_3V3 is required for proper operation. An additional 0.1 μF capacitor in parallel with CLDO_3V3 is highly recommended to filter high frequency noise from the I/O buffers and PHYs. The LDO_3V3 can supply external circuits at up to 25 mA. Expected loads include: EEPROM (5mA), NTC resistor divider network (< 1 mA). Current may be drawn up to ILDO_3V3(ILIMIT). Note: the USB PD and Endpoint PHYs draw current from LDO_3V3. If a CCx or Dx pin is shorted to GND during a transmission the current drawn may reach the current limit threshold. Similarly, if any GPIO pins are configured as push-pull outputs and a GPIO short to GND event occurs, the LDO_3V3 current limit may be reached. Current returns to AGND pin.
  • LDO_1V5: Supplies digital core. External bypass capacitance of CLDO_1V5 is required for proper operation. An additional 0.1 μF capacitor in parallel with CLDO_1V5 is highly recommended to filter noise generated by the digital core. The M0 is held in reset until all three UVLO_R (rising) thresholds are met. Current returns to AGND pin.

GUID-834E4CB8-957F-4E28-B771-2BB1C81A9855-low.gif Figure 9-3 Internal LDO Connection Diagram