SLAAER4 March   2025 AFE781H1 , AFE782H1 , AFE881H1 , AFE882H1 , DAC8740H , DAC8741H , DAC8742H

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 The 4-20mA Loop
    2. 1.2 The HART Protocol
      1. 1.2.1 Adding HART to the 4-20mA Loop
      2. 1.2.2 HART FSK
  5. 2AFE882H1 EVM-Based HART Transmitter
    1. 2.1 AFE882H1 HART Modem
    2. 2.2 AFE882H1 Evaluation Module
    3. 2.3 HART Transmitter Construction
      1. 2.3.1 Detailed Schematic
        1. 2.3.1.1 Input Protection
        2. 2.3.1.2 Start Up With Low-Dropout Regulator
        3. 2.3.1.3 Voltage-to-Current Stage
        4. 2.3.1.4 Voltage-to-Current Calculation
        5. 2.3.1.5 HART Signal Transmission
        6. 2.3.1.6 HART Input Protection
        7. 2.3.1.7 HART Transmitter Board
        8. 2.3.1.8 Current Consumption
      2. 2.3.2 HART Protocol Stack
  6. 3HART Testing and Registration
    1. 3.1  HART History and the FieldComm Group
    2. 3.2  HART Testing Overview
      1. 3.2.1 HART Protocol Specifications
      2. 3.2.2 HART Protocol Test Specifications
      3. 3.2.3 Field Transmitter Device Testing
    3. 3.3  HART Test Equipment
    4. 3.4  HART Physical Layer Testing
      1. 3.4.1 FSK Sinusoid Test
      2. 3.4.2 Carrier Start and Stop Time Tests
      3. 3.4.3 Carrier Start and Stop Transient Tests
      4. 3.4.4 Output Noise During Silence
      5. 3.4.5 Analog Rate of Change Test
      6. 3.4.6 Receive Impedance Test
      7. 3.4.7 Noise Sensitivity Test
      8. 3.4.8 Carrier Detect Test
    5. 3.5  Data Link Layer Tests
      1. 3.5.1 Data Link Layer Test Specifications
      2. 3.5.2 Data Link Layer Test Logs
    6. 3.6  Universal Command Tests
    7. 3.7  Common-Practice Command Tests
    8. 3.8  Device Specific Command Tests
    9. 3.9  HART Protocol Test Submission
    10. 3.10 HART Registration
  7. 4Summary
  8. 5Acknowledgments
  9. 6References

2.3.1.3 Voltage-to-Current Stage

Figure 2-6 shows a simplified schematic of the V-to-I stage of the transmitter. This stage sets the current of the loop based on the voltage output of the DAC.

Voltage-to-Current Converter Stage for the Transmitter Board Figure 2-9 Voltage-to-Current Converter Stage for the Transmitter Board

In this circuit, the DAC voltage is set across 120kΩ of equivalent resistance. The voltage at the opposite end of the 120kΩ is a virtual ground set by the feedback of the OPA333. The output of the OPA333 drives Q2 which sets the loop current.

The current flowing from VOUT, I1 combines with the current of I2. I2 is sourced from VREFIO across a 412kΩ resistor. This current contributes an offset to set the minimum current in the loop. The currents of I1 and I2 combine to set the voltage across a 20kΩ resistor below ground at LOOP–. The following equations show the voltage at LOOP–.

Equation 1. I1 = VOUT / 120kΩ
Equation 2. I2 = VREFIO / 412kΩ
Equation 3. –VLOOP– = (I1 + I2) × 20kΩ

I1 and I2 are pulled from ground to LOOP–. Current through the 20kΩ resistor is amplified 1000:1 in the 20Ω resistor shown in I3.

Equation 4. I3 = –VLOOP– / 20Ω = (I1 + I2) × 20kΩ / 20Ω = 1000 × (I1 + I2)

The loop current is the sum of the currents through these paths and can be calculated as a function of I1 and I2.

Equation 5. ILOOP– = I1 + I2 + I3 = 1001 × (I1 + I2)