SLAAER4 March   2025 AFE781H1 , AFE782H1 , AFE881H1 , AFE882H1 , DAC8740H , DAC8741H , DAC8742H

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 The 4-20mA Loop
    2. 1.2 The HART Protocol
      1. 1.2.1 Adding HART to the 4-20mA Loop
      2. 1.2.2 HART FSK
  5. 2AFE882H1 EVM-Based HART Transmitter
    1. 2.1 AFE882H1 HART Modem
    2. 2.2 AFE882H1 Evaluation Module
    3. 2.3 HART Transmitter Construction
      1. 2.3.1 Detailed Schematic
        1. 2.3.1.1 Input Protection
        2. 2.3.1.2 Start Up With Low-Dropout Regulator
        3. 2.3.1.3 Voltage-to-Current Stage
        4. 2.3.1.4 Voltage-to-Current Calculation
        5. 2.3.1.5 HART Signal Transmission
        6. 2.3.1.6 HART Input Protection
        7. 2.3.1.7 HART Transmitter Board
        8. 2.3.1.8 Current Consumption
      2. 2.3.2 HART Protocol Stack
  6. 3HART Testing and Registration
    1. 3.1  HART History and the FieldComm Group
    2. 3.2  HART Testing Overview
      1. 3.2.1 HART Protocol Specifications
      2. 3.2.2 HART Protocol Test Specifications
      3. 3.2.3 Field Transmitter Device Testing
    3. 3.3  HART Test Equipment
    4. 3.4  HART Physical Layer Testing
      1. 3.4.1 FSK Sinusoid Test
      2. 3.4.2 Carrier Start and Stop Time Tests
      3. 3.4.3 Carrier Start and Stop Transient Tests
      4. 3.4.4 Output Noise During Silence
      5. 3.4.5 Analog Rate of Change Test
      6. 3.4.6 Receive Impedance Test
      7. 3.4.7 Noise Sensitivity Test
      8. 3.4.8 Carrier Detect Test
    5. 3.5  Data Link Layer Tests
      1. 3.5.1 Data Link Layer Test Specifications
      2. 3.5.2 Data Link Layer Test Logs
    6. 3.6  Universal Command Tests
    7. 3.7  Common-Practice Command Tests
    8. 3.8  Device Specific Command Tests
    9. 3.9  HART Protocol Test Submission
    10. 3.10 HART Registration
  7. 4Summary
  8. 5Acknowledgments
  9. 6References

2.3 HART Transmitter Construction

Using the AFE882H1-FE-EVM, a HART transmitter can be constructed using a TI microprocessor with a LaunchPad connection. The DBE board from Figure 2-2 is replaced with a DBE board with a LaunchPad connector footprint (LP-DBE board). Figure 2-4 shows a MSP-EXP430FR5969 LaunchPad with a LP-DBE connector board. The LaunchPad is programmed with a basic stack used to control the loop current and respond to HART communication.

MSP-EXP430FR5969 LaunchPad with a LP-DBE Connector Board Figure 2-4 MSP-EXP430FR5969 LaunchPad with a LP-DBE Connector Board

Figure 2-5 shows the AFE882H1 HART block diagram transmitter design.

Block Diagram of a 2-wire Transmitter Design Using an AFE882H1 Evaluation Module and a Digital-Back-End Board Figure 2-5 Block Diagram of a 2-wire Transmitter Design Using an AFE882H1 Evaluation Module and a Digital-Back-End Board

The terminals connected to the loop are shown on the right side of the block diagram. This connection to the loop powers the entire transmitter. A bridge rectifier at the input protects against reverse connection to the loop. The rectified loop voltage powers a start-up circuit that provides power to a low-dropout regulator (LDO), that in turn powers the AFE882H1. The LDO powers the remainder of the circuit including a LaunchPad programmed with a HART stack.

HART communications are translated with the AFE882H1 HART modem. The device receives the HART signal through a capacitive coupled connection to the positive terminal side after the loop protection to the board. The HART signal is transmitted to the loop through the voltage-to-current (V-to-I) stage of the board.

Note that this transmitter board does not have a sensor to transmit data. The loop current is nominally set to 4mA as an output, except for specific HART tests. The main purpose of this board is to test the HART communication functionality of the AFE882H1.