SLVA888C April   2017  – January 2021 TPS65987D , TPS65988

 

  1.   Trademarks
  2. 1Schematic Design Guidelines
    1. 1.1  Power Supply Scheme
      1. 1.1.1 VIN_3V3
      2. 1.1.2 LDO_3V3
      3. 1.1.3 LDO_1V8
    2. 1.2  Boot Configuration
      1. 1.2.1 BUSPOWER (ADCIN1)
      2. 1.2.2 External SPI Flash
    3. 1.3  I2C Interface
      1. 1.3.1 I2C Pin Address Setting (ADCIN2)
    4. 1.4  HRESET
    5. 1.5  Configuration Channel / VCONN Lines
      1. 1.5.1 PP_CABLE
    6. 1.6  Battery Charger Detection and Advertisement (BC1.2)
    7. 1.7  GPIOs
    8. 1.8  Hot Plug Detect or HPD Line
    9. 1.9  PP_EXT Power Path Control
    10. 1.10 Power Path Considerations
  3. 2Layout Guidelines
    1. 2.1 Power Domain
    2. 2.2 Hi Speed Lines
    3. 2.3 Other Considerations
  4. 3Summary
  5. 4References
  6.   A Appendix
    1.     A.1 Dead Battery Considerations
    2.     A.2 TPS65987DDH Schematic Checklist
    3.     A.3 TPS65987DDH System Checklist
  7.   Revision History

2.1 Power Domain

This device is designed for PD power up to 60 W through the internal power paths and can support up to 100 W of power if external power FETs are used. Use these basic guidelines to avoid design issues:

  1. The use external FETs with big packages is preferred because they dissipate heat. During rapid temperature rise, smaller FETs can cause damage due to a short circuit. Bigger FETs can dissipate the heat much faster, and stay protected.
  2. Provide wide traces for all the high current paths like VBUS, PP_HV, PP_EXT to ensure a low resistance path or power plane for VBUS.
  3. Ensure enough free space and copper around the power devices to facilitate heat dissipation.
  4. Avoid any vias in high current path, but if required, then provide at least one via for every 500-mA current.
  5. Provide at-least 8 mills trace for CC lines to support high currents for VCONN supply.
  6. Place decoupling caps close to the power supply pin.
  7. Provide at-least eight vias for the ground pad beneath the chip. These vias should run from top layer to the bottom layer. These vias ensure good electrical and thermal conductivity and helps to dissipate heat generated in the chip.
  8. For the two split FET pads, provide at least 6 thermal vias underneath each pad. These vias must be electrically isolated (NC). Ensure these vias run from top layer to bottom layer and are preferably tented.