SLVA888C April   2017  – January 2021 TPS65987D , TPS65988

 

  1.   Trademarks
  2. 1Schematic Design Guidelines
    1. 1.1  Power Supply Scheme
      1. 1.1.1 VIN_3V3
      2. 1.1.2 LDO_3V3
      3. 1.1.3 LDO_1V8
    2. 1.2  Boot Configuration
      1. 1.2.1 BUSPOWER (ADCIN1)
      2. 1.2.2 External SPI Flash
    3. 1.3  I2C Interface
      1. 1.3.1 I2C Pin Address Setting (ADCIN2)
    4. 1.4  HRESET
    5. 1.5  Configuration Channel / VCONN Lines
      1. 1.5.1 PP_CABLE
    6. 1.6  Battery Charger Detection and Advertisement (BC1.2)
    7. 1.7  GPIOs
    8. 1.8  Hot Plug Detect or HPD Line
    9. 1.9  PP_EXT Power Path Control
    10. 1.10 Power Path Considerations
  3. 2Layout Guidelines
    1. 2.1 Power Domain
    2. 2.2 Hi Speed Lines
    3. 2.3 Other Considerations
  4. 3Summary
  5. 4References
  6.   A Appendix
    1.     A.1 Dead Battery Considerations
    2.     A.2 TPS65987DDH Schematic Checklist
    3.     A.3 TPS65987DDH System Checklist
  7.   Revision History

1.3.1 I2C Pin Address Setting (ADCIN2)

ADCIN2 pin is used to set the I2C address of the device. At boot time, the chip determines the voltage and sets the I2C address. A potential divider must be used between LDO_3V3 and GND to get the desired I2C address. I2C address of the I2C port 1 as per Table 1-2

GUID-20201220-CA0I-KGKF-7L4M-Z4BG66769KTP-low.jpgFigure 1-4 ADCIN2 Resistor Divided Network.

Important: External resistor tolerance of 1% is required.

A potential divider must be used between LDO_3V3 and GND to get the desired I2C address. I2C address of the I2C port 1 as per Table 1-2.

Table 1-2 I2C Address of the I2C Port 1
DIV = R2/(R1 + R2)Default Unique Address I2C1 – Port1 (7-bit)Default Unique Address I2C1 – Port2

Resistor Recommendation

DIV MINDIV MAX
Short ADCIN2 to GND 0x200x24

R2=100K

0.200.380x210x25

R1=191K

R2=100K

0.400.580x220x26

R1=100K

R2=100K

Short ADCIN2 to LDO_3V3 0x230x27

R1=100K