SLVUDB9 July   2025 ADC34RF72

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware and Software Setup
    1. 2.1  Board Overview
    2. 2.2  Required Equipment
    3. 2.3  Required Software Installation
    4. 2.4  Required TI Software to Install
    5. 2.5  3rd Party Software to Install
    6. 2.6  Software Environment Setup
    7. 2.7  Hardware Setup and Connections
    8. 2.8  ADC3xRF72 EVM Connections
    9. 2.9  TSW14J58 Data Capture Card Connections
    10. 2.10 Debug LEDs
    11. 2.11 EVM Jumpers and Switches
  9. 3ADC3xRF72 EVM Configuration and Programming
    1. 3.1  ADC EVM Quick Start
    2. 3.2  Power on all Boards and Signal Generators
    3. 3.3  Launch GSPS FPGA Server
    4. 3.4  Launch High-Speed Data Converter Professional (HSDC Pro) SW
    5. 3.5  Programming the ADC
    6. 3.6  Quick Start Mode
    7. 3.7  System Level Configuration Mode
    8. 3.8  Advanced Mode
    9. 3.9  Runtime Configuration
    10. 3.10 Exporting ADC3xRF72 Configuration and Python API usage
    11. 3.11 Further GUI Help
  10. 4Troubleshooting and FAQ
  11. 5Important Signal Routing
    1. 5.1 ADC Device Clock Routing
    2. 5.2 Board Modifications
      1. 5.2.1 ADC3xRF72 Analog Inputs
  12. 6Hardware Design Files
    1. 6.1 Schematics
    2. 6.2 PCB Layouts
    3. 6.3 Bill of Materials (BOM)
  13. 7Additional Information
    1. 7.1 Trademarks
  14. 8References

Features

  • Noise spectral density: -164.2 dBFS/Hz
  • Full power input bandwidth (-3dB): 1.8GHz
  • Power consumption: 0.95 W/channel (1.5GSPS)
  • Eight digital down-converters, can be configured in single band, dual band and octal band configurations. Supporting real and complex decimation with factors starting at /2,/3,/5 up to 32768.
  • 48-bit NCO phase coherent frequency hopping
  • Serial JESD interface supporting lane rate up to 24.75Gbps
  • Multiple integrated DSP features such as 96-tap/ch PFIR equalizer an fractional delay filter