The test setup for GPIO SET testing is shown in Block Diagram for GPIO Test Configuration.

The execution code was loaded into the flash memory of the F28377D device, giving the device ability to re-boot into the test code should a fault occur within the code execution itself, relying on the internal watchdog and NMI logic of the device. A "heartbeat" signal at was also brought out in the GPIOs in order to determine if the code was executing correctly. This signal served a dual purpose, both to measure during Ion beam exposure, but also show that the device can recover from a transient event. The GPIOs on the F28377D-SEP device were configured and tested as follows:

• Output
  • GPIO output toggled at various frequencies using CPU timer to identify the susceptibility of various timed events in the space mission that potentially employ the CPU timer.
  • GPIO output held at a static value of “0” or “1” to identify the data retention capability of the GPIO data registers. This configuration also helps in identifying the transient effects induced on the pin due to heavy ions.
  • •GPIO output toggled using a software timer in the program code. The main goal of this configuration is to validate the continuous CPU execution analogous to a heartbeat
• Input
  • XINT triggered by rising and falling edges of the input signal fed into the pins using signal generator at varying frequencies. This configuration tests how well the input fed through the pins is read during the operation. This also evaluates how well time critical external interrupts are serviced in the radiation prone service environment.

The fault modeling for each of the tests can be seen in the following figures; CPU Timer Fault Modeling, Figure 8-3, and Figure 8-4.