SPRK066 October   2025 F28377D-SEP

 

  1.   1
  2.   F28377D-SEP Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Single-Event Effects (SEE)
  6. 3Device and Test Board Information
  7. 4Irradiation Facility and Setup
  8. 5Depth, Range, and LETEFF Calculation
  9. 6Test Setup and Procedures
  10. 7Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
  11. 8Single-Event Transients (SET)
    1. 8.1 GPIO Testing and Results
      1. 8.1.1 GPIO Test Setup
      2. 8.1.2 GPIO SET Analysis
      3. 8.1.3 GPIO SET Summary
    2. 8.2 ePWM Testing and Results
      1. 8.2.1 ePWM Testing Setup
      2. 8.2.2 ePWM SET Analysis
      3. 8.2.3 ePWM SET Summary
    3. 8.3 SRAM Testing and Results
      1. 8.3.1 SRAM Test Setup
      2. 8.3.2 SRAM SET Summary
    4. 8.4 Flash Memory Testing and Results
      1. 8.4.1 Flash Test Setup
      2. 8.4.2 Flash SET Summary
  12. 9Summary
  13.   A Total Ionizing Dose from SEE Experiments
  14.   B References

8.2.1 ePWM Testing Setup

The test setup for ePWM SET testing is show in Figure 8-7.

TMS320F38377D-SEP Block Diagram for ePWM Test Configuration Figure 8-7 Block Diagram for ePWM Test Configuration

The execution code was loaded into the flash memory of the F28377D device, giving the device ability to re-boot into the test code should a fault occur within the code execution itself, relying on the internal watchdog and NMI logic of the device. A "heartbeat" signal at was also brought out in the GPIOs in order to determine if the code was executing correctly. This signal served a dual purpose, both to measure during Ion beam exposure, but also show that the device can recover from a transient event.

Twelve PWM signals were brought to the device pins, consisting of 6 PWM modules with the A and B channels of each module comprising the 12 signals. The phase of wave A is complementary to wave B, and both were monitored for consistency to one another in addition to the correct frequency.

Deadband of 200ns was inserted on channels 4B and 7B on the falling edge of the A output to test the deadband logic. The summary of the different test runs are shown in Table 8-3.

Table 8-3 GPIO System Test Configuration Details
Runs PWM Channels Frequency Duty Cycle Dead Band Inserted
3 12 1kHz 10 No
50
90
2 1kHz 10 200ns
50
90
12 10kHz 10 No
50
90
2 10kHz 10 200ns
50
90
12 100kHz 10 No
50
90
2 100kHz 10 200ns
50
90

The fault modeling for the PWM testing is shown below Figure 8-8.

TMS320F38377D-SEP PWM Fault Modeling Figure 8-8 PWM Fault Modeling