SPRK066 October   2025 F28377D-SEP

 

  1.   1
  2.   F28377D-SEP Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Single-Event Effects (SEE)
  6. 3Device and Test Board Information
  7. 4Irradiation Facility and Setup
  8. 5Depth, Range, and LETEFF Calculation
  9. 6Test Setup and Procedures
  10. 7Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
  11. 8Single-Event Transients (SET)
    1. 8.1 GPIO Testing and Results
      1. 8.1.1 GPIO Test Setup
      2. 8.1.2 GPIO SET Analysis
      3. 8.1.3 GPIO SET Summary
    2. 8.2 ePWM Testing and Results
      1. 8.2.1 ePWM Testing Setup
      2. 8.2.2 ePWM SET Analysis
      3. 8.2.3 ePWM SET Summary
    3. 8.3 SRAM Testing and Results
      1. 8.3.1 SRAM Test Setup
      2. 8.3.2 SRAM SET Summary
    4. 8.4 Flash Memory Testing and Results
      1. 8.4.1 Flash Test Setup
      2. 8.4.2 Flash SET Summary
  12. 9Summary
  13.   A Total Ionizing Dose from SEE Experiments
  14.   B References

8.3.2 SRAM SET Summary

The SRAM transient event count is shown in Table 8-7 Key takeaways from the data are:
  • ECC protected SRAM(Mx and Dx RAMs) are two orders of magnitude less susceptible to transient upsets. This implies that during the read/write duration the majority of upsets are single bit correctable errors
  • Due to the nature of ECC implementation on SRAMs, a correctable error is not only corrected prior to use by the CPU, but the corrected value is also written back to the SRAM avoiding aggregated errors
  • Parity protected SRAM(LSx and GSx), while observing more failures than the ECC protected RAMs, will be able to detect most transients due to their single bit nature.
  • While all SRAMs are constructed similarly, it is important to keep in mind that due to size and number of instances that GSx SRAM will have a higher probability of transient events based on its on die area.
Table 8-7 SRAM Transient Upset Summary
SRAM Type LETEFF(MeV·cm2/mg Ion Type Bit Flips Bit Total Fluence (# of ions) Cross Section(Event Count/LETEFF
Mx and Dx (ECC) RAMs 45 109Ag 0 98304 1.00 E6 1.85 E-61
Mx and Dx (ECC) RAMs 8.5 40Ar 0 98304 1.01 E6 6.07 E-71
LSx and GSx(Parity) RAMs 45 109Ag 3230 1,245,84 1.00 E6 2.27 E-4
LSx and GSx(Parity) RAMs 8.5 40Ar 521 1,245,84 1.01 E6 3.47 E-5
  1. Since there were no upsets observed the cross section for this section is calculated as a Mean Fluence To Fail (MFTF) at 95% confidence interval based on the average fluence of the runs. See Single-Event Effects Confidence Interval Calculations for more information on this calculation.