SPRK066 October 2025 F28377D-SEP
The F28377D-SEP is fabricated in the TI CMOS 65nm process with a back-end-of-line (BEOL) stack consisting of 7 levels of standard thickness aluminum. The total stack height from the surface of the passivation to the silicon surface is 380μm based on nominal layer thickness as shown in Figure 5-1. Accounting for energy loss through the 1-mil thick Aramica beam port window, the 40-mm air gap, and the BEOL stack over the F28377D-SEP, the effective LET (LETEFF) at the surface of the silicon substrate and the depth was determined with the SEUSS 2020 Software (provided by the Texas A&M Cyclotron Institute and based on the latest SRIM-2013 [7] models). The results are shown in Ion LETEFF, Depth, and Range in Silicon.
| ION TYPE | Beam Energy (MeV/nucleon) | ANGLE OF INCIDENCE | DEGRADER STEPS (#) | DEGRADER ANGLE | RANGE
IN SILICON (µm) |
LETEFF (MeV·cm2/mg) |
|---|---|---|---|---|---|---|
| 109Ag | 15 | 0 | 0 | 0 | 111.2 | 45 |
| 40Ar | 15 | 0 | 0 | 0 | 196.8 | 8 |