SPRK066 October   2025 F28377D-SEP

 

  1.   1
  2.   F28377D-SEP Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Single-Event Effects (SEE)
  6. 3Device and Test Board Information
  7. 4Irradiation Facility and Setup
  8. 5Depth, Range, and LETEFF Calculation
  9. 6Test Setup and Procedures
  10. 7Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
  11. 8Single-Event Transients (SET)
    1. 8.1 GPIO Testing and Results
      1. 8.1.1 GPIO Test Setup
      2. 8.1.2 GPIO SET Analysis
      3. 8.1.3 GPIO SET Summary
    2. 8.2 ePWM Testing and Results
      1. 8.2.1 ePWM Testing Setup
      2. 8.2.2 ePWM SET Analysis
      3. 8.2.3 ePWM SET Summary
    3. 8.3 SRAM Testing and Results
      1. 8.3.1 SRAM Test Setup
      2. 8.3.2 SRAM SET Summary
    4. 8.4 Flash Memory Testing and Results
      1. 8.4.1 Flash Test Setup
      2. 8.4.2 Flash SET Summary
  12. 9Summary
  13.   A Total Ionizing Dose from SEE Experiments
  14.   B References

8.3.1 SRAM Test Setup

The test setup for SRAM is shown in Figure 8-14.

TMS320F38377D-SEP Block Diagram for SRAM Test Configuration Figure 8-14 Block Diagram for SRAM Test Configuration

For this test, the C28x CPU was used to read and write to the SRAM. To avoid transient upsets to that logic as well as any other logic not under test, a mask was used to block the ion beam from any other logic other than the SRAM under test. The F28377D-SEP does not allow for ECC or Parity disable for the on-chip SRAM. In the case of parity protected SRAMs this would not limit the detected errors, for ECC protected errors, any single bit error, for example a correctable error, is ignored from the failure rate. Both scenarios match the end use case, and as such the data can be used directly to determine the failure rate during mission. Table 8-6 gives the details of the various tests that were ran during the transient testing.

Table 8-6 SRAM Test Configuration
Runs Test Type Target Memory WR+RD Frequency
3 Dynamic MX and DX RAM Write and Read all SRAMs every 100μs
3 Dynamic GX RAM Write and Read all SRAMs every 100μs