SWCU185F january 2018 – march 2023 CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1
Table 20-270 lists the memory-mapped registers for the AUX_SCE registers. All register offset addresses not listed in Table 20-270 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0h | CTL | Internal | CTL Register (Offset = 0h) [Reset = 00000000h] |
4h | FETCHSTAT | Internal | FETCHSTAT Register (Offset = 4h) [Reset = 00000000h] |
8h | CPUSTAT | Internal | CPUSTAT Register (Offset = 8h) [Reset = 00000000h] |
Ch | WUSTAT | Internal | WUSTAT Register (Offset = Ch) [Reset = 00000000h] |
10h | REG1_0 | Internal | REG1_0 Register (Offset = 10h) [Reset = 00000000h] |
14h | REG3_2 | Internal | REG3_2 Register (Offset = 14h) [Reset = 00000000h] |
18h | REG5_4 | Internal | REG5_4 Register (Offset = 18h) [Reset = 00000000h] |
1Ch | REG7_6 | Internal | REG7_6 Register (Offset = 1Ch) [Reset = 00000000h] |
20h | LOOPADDR | Internal | LOOPADDR Register (Offset = 20h) [Reset = 00000000h] |
24h | LOOPCNT | Internal | LOOPCNT Register (Offset = 24h) [Reset = 00000000h] |
Complex bit access types are encoded to fit into small table cells. Table 20-271 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
Write Type | ||
W | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |
CTL is shown in Figure 20-244 and described in Table 20-272.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
FORCE_EV_LOW | |||||||
R/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
FORCE_EV_HIGH | |||||||
R/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESET_VECTOR | |||||||
R/W-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DBG_FREEZE_EN | FORCE_WU_LOW | FORCE_WU_HIGH | RESTART | SINGLE_STEP | SUSPEND | CLK_EN |
R-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-24 | FORCE_EV_LOW | R/W | 0h | Internal. Only to be used through TI provided API. |
23-16 | FORCE_EV_HIGH | R/W | 0h | Internal. Only to be used through TI provided API. |
15-8 | RESET_VECTOR | R/W | 0h | Internal. Only to be used through TI provided API. |
7 | RESERVED | R | 0h | Reserved |
6 | DBG_FREEZE_EN | R/W | 0h | Internal. Only to be used through TI provided API. |
5 | FORCE_WU_LOW | R/W | 0h | Internal. Only to be used through TI provided API. |
4 | FORCE_WU_HIGH | R/W | 0h | Internal. Only to be used through TI provided API. |
3 | RESTART | R/W | 0h | Internal. Only to be used through TI provided API. |
2 | SINGLE_STEP | R/W | 0h | Internal. Only to be used through TI provided API. |
1 | SUSPEND | R/W | 0h | Internal. Only to be used through TI provided API. |
0 | CLK_EN | R/W | 0h | Internal. Only to be used through TI provided API. |
FETCHSTAT is shown in Figure 20-245 and described in Table 20-273.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OPCODE | PC | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | OPCODE | R | 0h | Internal. Only to be used through TI provided API. |
15-0 | PC | R | 0h | Internal. Only to be used through TI provided API. |
CPUSTAT is shown in Figure 20-246 and described in Table 20-274.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | BUS_ERROR | SLEEP | WEV | HALTED | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | V_FLAG | C_FLAG | N_FLAG | Z_FLAG | |||
R-0h | R-0h | R-0h | R-0h | R-0h | |||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-12 | RESERVED | R | 0h | Reserved |
11 | BUS_ERROR | R | 0h | Internal. Only to be used through TI provided API. |
10 | SLEEP | R | 0h | Internal. Only to be used through TI provided API. |
9 | WEV | R | 0h | Internal. Only to be used through TI provided API. |
8 | HALTED | R | 0h | Internal. Only to be used through TI provided API. |
7-4 | RESERVED | R | 0h | Reserved |
3 | V_FLAG | R | 0h | Internal. Only to be used through TI provided API. |
2 | C_FLAG | R | 0h | Internal. Only to be used through TI provided API. |
1 | N_FLAG | R | 0h | Internal. Only to be used through TI provided API. |
0 | Z_FLAG | R | 0h | Internal. Only to be used through TI provided API. |
WUSTAT is shown in Figure 20-247 and described in Table 20-275.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | EXC_VECTOR | ||||||
R-0h | R-0h | ||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | WU_SIGNAL | ||||||
R-0h | R-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
EV_SIGNALS | |||||||
R-0h | |||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-19 | RESERVED | R | 0h | Reserved |
18-16 | EXC_VECTOR | R | 0h | Internal. Only to be used through TI provided API. |
15-9 | RESERVED | R | 0h | Reserved |
8 | WU_SIGNAL | R | 0h | Internal. Only to be used through TI provided API. |
7-0 | EV_SIGNALS | R | 0h | Internal. Only to be used through TI provided API. |
REG1_0 is shown in Figure 20-248 and described in Table 20-276.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG1 | REG0 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | REG1 | R | 0h | Internal. Only to be used through TI provided API. |
15-0 | REG0 | R | 0h | Internal. Only to be used through TI provided API. |
REG3_2 is shown in Figure 20-249 and described in Table 20-277.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG3 | REG2 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | REG3 | R | 0h | Internal. Only to be used through TI provided API. |
15-0 | REG2 | R | 0h | Internal. Only to be used through TI provided API. |
REG5_4 is shown in Figure 20-250 and described in Table 20-278.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG5 | REG4 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | REG5 | R | 0h | Internal. Only to be used through TI provided API. |
15-0 | REG4 | R | 0h | Internal. Only to be used through TI provided API. |
REG7_6 is shown in Figure 20-251 and described in Table 20-279.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
REG7 | REG6 | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | REG7 | R | 0h | Internal. Only to be used through TI provided API. |
15-0 | REG6 | R | 0h | Internal. Only to be used through TI provided API. |
LOOPADDR is shown in Figure 20-252 and described in Table 20-280.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STOP | START | ||||||||||||||||||||||||||||||
R-0h | R-0h | ||||||||||||||||||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | STOP | R | 0h | Internal. Only to be used through TI provided API. |
15-0 | START | R | 0h | Internal. Only to be used through TI provided API. |
LOOPCNT is shown in Figure 20-253 and described in Table 20-281.
Return to the Summary Table.
Internal. Only to be used through TI provided API.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||||||||||
R-0h | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ITER_LEFT | ||||||||||||||
R-0h | R-0h | ||||||||||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-8 | RESERVED | R | 0h | Reserved |
7-0 | ITER_LEFT | R | 0h | Internal. Only to be used through TI provided API. |