On the isolation side of the test board, a high-voltage 3-kV, 2.2-nF capacitor in parallel with a 2.2-kV, 3.3-MΩ resistor is placed between the protected ground and the earth ground for providing a path to discharge the transient energy. There are two discharge paths on the isolation side. The same scheme is used in the non-isolation area on the test board.

The 49.9-Ω damping resistors on the digital lines between the ADS8686S and the precision host interface (PHI) controller board are designed to attenuate the electrical transient signals and slow down fast logic edges to minimize EMI (Electromagnetic Interference) or RFI (Radio Frequency Interference) problems.

The decoupling capacitors are placed as close as possible next to the device where it requires decoupling, and they are connected to the ground plane using vias. Power planes are used instead of individual traces to reduce the inductance and provide better decoupling to the ground plane.

The ADS8686S is a single-ended input ADC; however, it samples the difference between the positive pin (AIN_nA/B) and the negative input pin (AIN_nA/BGND). In this design, the traces for these two signals in each channel are routed closely to each other as a differential pair so that any external any interference and noise intervening with these two traces add the same amount of disturbance into both traces. Therefore, the induced noise signal is a common-mode signal which the ADC will reject within the common-mode rejection ratio (CMRR) specification limits.

The vias or via holes in multilayer PCBs should be avoided as much as possible because each via introduces capacitance and inductance. Also, the critical traces such as clocks should be routed on the same layer without the use of a via to minimize radio frequency (RF) emissions and susceptibility. In this design, no via is used for analog signal routing purposes across layers and all traces for analog signals are routed on the top layer.

The ADS8686S EMC test board is built on a four-layer PCB which is a minimum stack-up as a practical recommendation. The second layer is the inner ground (GND and IGND) layer for good decoupling and ground returns as an adjacent layer. The noise on the power and ground planes that reaches the edge of the circuit board can radiate out of the board. The guard ring on the PCB edge surrounding the entire circuit board is a grounding technique that can reflect the noise back into the circuit board and isolate the noisy environment outside of the ring because there is no current flowing through the guard ring in a normal operation. The guard ring is usually connected to the chassis and earth ground. The guard ring on the ADS8686S EMC test board is designed on both top and bottom layers, and the edge guard on these layers are linked together with vias every 100-mil space to attenuate emissions of high frequency signals up to GHz.

The space across the isolation barrier on the EMC test board is designed as wide as possible to maintain high-voltage isolation requirements for IEC testing. The plane that is exposed at the edge of a PCB board can provide a breakdown path especially when the plane is terminated at the edge of the circuit board in a sharp corner shape, where it enhances electric fields and becomes a location for arcing. A good PCB design example in Figure 2-2 shows that the sharp corners of inner planes are rounded off and the planes are moved back from the edge to enhance the isolation design and avoid potential breakdowns.